Haswell/falco/peppy/slippy: continue to clean up FUI.

As a first step towards removing hardcodes from the FUI support,
change the haswell call to i915_lightup to panel_lightup, and pass the
intel_dp * as a parameter. Get rid of the scalar arguments and make
them part of intel_dp. Get rid of file-scope variables and use the
ones in the intel_dp struct. In falco, use functions that peppy
uses. Drop slippy support for FUI, it's a dead board; if this is ok
I'll remove the files next.

And, incidentally, fix the broken RGBX constant and change it to BGRX.

Change-Id: I46ef5a9ed8433382d042066ee3542af04cfc319a
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/174932
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
(cherry picked from commit 1e1ed410b445c8e2b7411e163d9d6f61499dc3f6)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6833
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

src/drivers/intel/gma/i915.h

@@ -175,6 +175,12 @@ struct intel_dp {
 	struct intel_dp_m_n m_n;
 	u32 flags;
 	u32 transcoder;
+	/* parameters computed by the early startup, to be used
+	 * in the GMA code.
+	 */
+	u8 *graphics;
+	/* physical address, not to be used directly. */
+	u64 physbase;
 };
 
 /* we may yet need these. */
@@ -278,6 +284,7 @@ u32 gtt_read(u32 reg);
 
 int i915lightup(unsigned int physbase, unsigned int mmio,
 		unsigned int gfx, unsigned int init_fb);
+int panel_lightup(struct intel_dp *dp, unsigned int init_fb);
 
 /* display.c */
 void compute_display_params(struct intel_dp *dp);

src/mainboard/google/falco/gma.c

@@ -43,6 +43,7 @@
 #include <cpu/x86/msr.h>
 #include <edid.h>
 #include <drivers/intel/gma/i915.h>
+#include <northbridge/intel/haswell/haswell.h>
 #include "mainboard.h"
 
 /*
@@ -86,52 +87,6 @@
  */
 #define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
 
-static unsigned int *mmio;
-static unsigned int graphics;
-static unsigned int physbase;
-
-void ug1(int);
-void ug2(int);
-void ug22(int);
-void ug3(int);
-
-/* GTT is the Global Translation Table for the graphics pipeline.
- * It is used to translate graphics addresses to physical
- * memory addresses. As in the CPU, GTTs map 4K pages.
- * The setgtt function adds a further bit of flexibility:
- * it allows you to set a range (the first two parameters) to point
- * to a physical address (third parameter);the physical address is
- * incremented by a count (fourth parameter) for each GTT in the
- * range.
- * Why do it this way? For ultrafast startup,
- * we can point all the GTT entries to point to one page,
- * and set that page to 0s:
- * memset(physbase, 0, 4096);
- * setgtt(0, 4250, physbase, 0);
- * this takes about 2 ms, and is a win because zeroing
- * the page takes a up to 200 ms.
- * This call sets the GTT to point to a linear range of pages
- * starting at physbase.
- */
-
-#define GTT_PTE_BASE (2 << 20)
-
-static void
-setgtt(int start, int end, unsigned long base, int inc)
-{
-	int i;
-
-	for(i = start; i < end; i++){
-		u32 word = base + i*inc;
-		/* note: we've confirmed by checking
-		 * the values that mrc does no
-		 * useful setup before we run this.
-		 */
-		gtt_write(GTT_PTE_BASE + i * 4, word|1);
-		gtt_read(GTT_PTE_BASE + i * 4);
-	}
-}
-
 static int i915_init_done = 0;
 
 /* fill the palette. */
@@ -145,75 +100,6 @@ static void palette(void)
 	}
 }
 
-void dp_init_dim_regs(struct intel_dp *dp);
-void dp_init_dim_regs(struct intel_dp *dp)
-{
-	struct edid *edid = &(dp->edid);
-
-	dp->bytes_per_pixel = edid->framebuffer_bits_per_pixel / 8;
-
-	dp->stride = edid->bytes_per_line;
-
-	dp->htotal = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
-
-	dp->hblank = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
-
-	dp->hsync = (edid->ha + edid->hso - 1) |
-		((edid->ha + edid->hso + edid->hspw - 1) << 16);
-
-	dp->vtotal = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
-
-	dp->vblank = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
-
-	dp->vsync = (edid->va + edid->vso - 1) |
-		((edid->va + edid->vso + edid->vspw - 1) << 16);
-
-	/* PIPEASRC is wid-1 x ht-1 */
-	dp->pipesrc = (edid->ha-1)<<16 | (edid->va-1);
-
-	dp->pfa_pos = 0;
-
-	dp->pfa_ctl = 0x80800000;
-
-	dp->pfa_sz = (edid->ha << 16) | (edid->va);
-
-	dp->flags = intel_ddi_calc_transcoder_flags(3 * 6,  /* bits per color is 6 */
-						    dp->port,
-						    dp->pipe,
-						    dp->type,
-						    dp->lane_count,
-						    dp->pfa_sz,
-						    dp->edid.phsync == '+'?1:0,
-						    dp->edid.pvsync == '+'?1:0);
-
-	dp->transcoder = intel_ddi_get_transcoder(dp->port,
-						  dp->pipe);
-
-	intel_dp_compute_m_n(dp->pipe_bits_per_pixel,
-			     dp->lane_count,
-			     dp->edid.pixel_clock,
-			     dp->edid.link_clock,
-			     &dp->m_n);
-
-	printk(BIOS_SPEW, "dp->stride  = 0x%08x\n",dp->stride);
-	printk(BIOS_SPEW, "dp->htotal  = 0x%08x\n", dp->htotal);
-	printk(BIOS_SPEW, "dp->hblank  = 0x%08x\n", dp->hblank);
-	printk(BIOS_SPEW, "dp->hsync   = 0x%08x\n", dp->hsync);
-	printk(BIOS_SPEW, "dp->vtotal  = 0x%08x\n", dp->vtotal);
-	printk(BIOS_SPEW, "dp->vblank  = 0x%08x\n", dp->vblank);
-	printk(BIOS_SPEW, "dp->vsync   = 0x%08x\n", dp->vsync);
-	printk(BIOS_SPEW, "dp->pipesrc = 0x%08x\n", dp->pipesrc);
-	printk(BIOS_SPEW, "dp->pfa_pos = 0x%08x\n", dp->pfa_pos);
-	printk(BIOS_SPEW, "dp->pfa_ctl = 0x%08x\n", dp->pfa_ctl);
-	printk(BIOS_SPEW, "dp->pfa_sz  = 0x%08x\n", dp->pfa_sz);
-	printk(BIOS_SPEW, "dp->link_m  = 0x%08x\n", dp->m_n.link_m);
-	printk(BIOS_SPEW, "dp->link_n  = 0x%08x\n", dp->m_n.link_n);
-	printk(BIOS_SPEW, "0x6f030     = 0x%08x\n", TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m);
-	printk(BIOS_SPEW, "0x6f030     = 0x%08x\n", dp->m_n.gmch_m);
-	printk(BIOS_SPEW, "0x6f034     = 0x%08x\n", dp->m_n.gmch_n);
-	printk(BIOS_SPEW, "dp->flags   = 0x%08x\n", dp->flags);
-}
-
 void mainboard_train_link(struct intel_dp *intel_dp)
 {
 	u8 read_val;
@@ -289,25 +175,14 @@ void mainboard_set_port_clk_dp(struct intel_dp *intel_dp)
 	gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel);
 }
 
-int i915lightup(unsigned int pphysbase, unsigned int pmmio,
+int panel_lightup(struct intel_dp *dp, unsigned int init_fb)
-		unsigned int pgfx, unsigned int init_fb)
 {
-	int must_cycle_power = 0;
-	struct intel_dp adp, *dp = &adp;
 	int i;
 	int edid_ok;
 	int pixels = FRAME_BUFFER_BYTES/64;
 
-	mmio = (void *)pmmio;
-	physbase = pphysbase;
-	graphics = pgfx;
-	printk(BIOS_SPEW,
-	       "i915lightup: graphics %p mmio %p"
-	       "physbase %08x\n",
-	       (void *)graphics, mmio, physbase);
-
 	void runio(struct intel_dp *dp);
-	void runlinux(struct intel_dp *dp);
+
 	dp->gen = 8; // This is gen 8 which we believe is Haswell
 	dp->is_haswell = 1;
 	dp->DP = 0x2;
@@ -332,11 +207,12 @@ int i915lightup(unsigned int pphysbase, unsigned int pmmio,
 	   all GTT entries point to the same page
 	   2. Developer/Recovery mode: We do not zero out all
 	   the pages pointed to by GTT in order to avoid wasting time */
-        if (init_fb)
+        if (init_fb){
-                setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
+		set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 4096);
-        else {
+		memset((void *)dp->graphics, 0x55, FRAME_BUFFER_PAGES*4096);
-                setgtt(0, FRAME_BUFFER_PAGES, physbase, 0);
+        } else {
-                memset((void*)graphics, 0, 4096);
+                set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 0);
+                memset((void*)dp->graphics, 0, 4096);
         }
 
 	dp->address = 0x50;
@@ -355,11 +231,7 @@ int i915lightup(unsigned int pphysbase, unsigned int pmmio,
 	edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid);
 	printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok);
 
-	dp->edid.link_clock = intel_dp_bw_code_to_link_rate(dp->link_bw);
+	compute_display_params(dp);
-
-	printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n",dp->edid.pixel_clock, dp->edid.link_clock);
-
-	dp_init_dim_regs(dp);
 
 	intel_ddi_set_pipe_settings(dp);
 
@@ -372,18 +244,12 @@ int i915lightup(unsigned int pphysbase, unsigned int pmmio,
 
 	test_gfx(dp);
 
-	set_vbe_mode_info_valid(&dp->edid, graphics);
+	set_vbe_mode_info_valid(&dp->edid, (uintptr_t)dp->graphics);
 	i915_init_done = 1;
 	return i915_init_done;
 
 fail:
 	printk(BIOS_SPEW, "Graphics could not be started;");
-	if (0 && must_cycle_power){
-		printk(BIOS_SPEW, "Turn off power and wait ...");
-		gtt_write(PCH_PP_CONTROL,0xabcd0000);
-		udelay(600000);
-		gtt_write(PCH_PP_CONTROL,0xabcd000f);
-	}
 	printk(BIOS_SPEW, "Returning.\n");
 	return 0;
 }

src/mainboard/google/falco/i915io.c

@@ -28,12 +28,6 @@
 #include <arch/io.h>
 #include "mainboard.h"
 
-/* these variables will be removed when the proper support is finished in src/drivers/intel/gma/intel_dp.c */
-int index;
-u32 auxout;
-u8 auxin[20];
-u8 msg[32];
-
 /* this function will either be renamed or subsumed into ./gma.c:i915_lightup */
 void runio(struct intel_dp *dp);
 
@@ -72,7 +66,7 @@ void runio(struct intel_dp *dp)
 
 	mainboard_set_port_clk_dp(dp);
 	gtt_write(DSPSTRIDE(dp->plane),dp->stride);
-	gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_RGBX888);
+	gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_BGRX888);
 	gtt_write(DEIIR,0x00000080);
 
 	gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags);
@@ -125,7 +119,7 @@ void runio(struct intel_dp *dp)
 	intel_dp_wait_reg(DEIIR, 0x00000000);
 
 	gtt_write(DSPSTRIDE(dp->plane),dp->stride);
-	gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_RGBX888);
+	gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
 
 	gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON);
 

src/mainboard/google/falco/mainboard.h

@@ -0,0 +1,25 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright 2013 Google Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; version 2 of the License.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef __MAINBOARD_H_
+#define __MAINBOARD_H_
+void mainboard_train_link(struct intel_dp *intel_dp);
+void mainboard_set_port_clk_dp(struct intel_dp *intel_dp);
+
+#endif

src/mainboard/google/link/i915.c

@@ -374,7 +374,7 @@ int i915lightup(const struct northbridge_intel_sandybridge_config *info,
 		(void *)graphics, FRAME_BUFFER_BYTES);
 	memset((void *)graphics, 0, FRAME_BUFFER_BYTES);
 	printk(BIOS_SPEW, "%ld microseconds\n", globalmicroseconds());
-	set_vbe_mode_info_valid(&edid, graphics);
+	set_vbe_mode_info_valid(&edid, (uintptr_t)graphics);
 	i915_init_done = 1;
 	return i915_init_done;
 }

src/mainboard/google/peppy/gma.c

@@ -87,9 +87,6 @@
  */
 #define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
 
-static unsigned int *mmio;
-static unsigned int graphics;
-static unsigned int physbase;
 
 static int i915_init_done = 0;
 
@@ -155,8 +152,6 @@ static void test_gfx(struct intel_dp *dp)
 	   green and blue. It is very useful to ensure all the initializations
 	   are made right. Thus, to be used only for testing, not otherwise
 	*/
-	printk(BIOS_SPEW, "TEST: graphics %p, va %d, ha %d, stride %d\n",
-		(u32 *)graphics, dp->edid.va, dp->edid.ha, dp->stride);
 
 	for (i = 0; i < (dp->edid.va - 4); i++) {
 		u32 *l;
@@ -166,7 +161,7 @@ static void test_gfx(struct intel_dp *dp)
 			if (j == (dp->edid.ha/2)) {
 				tcolor = 0xff00;
 			}
-			l = (u32*)(graphics + i * dp->stride + j * sizeof(tcolor));
+			l = (u32*)(dp->graphics + i * dp->stride + j * sizeof(tcolor));
 			memcpy(l,&tcolor,sizeof(tcolor));
 		}
 	}
@@ -196,24 +191,14 @@ void mainboard_set_port_clk_dp(struct intel_dp *intel_dp)
 	gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel);
 }
 
-int i915lightup(unsigned int pphysbase, unsigned int pmmio,
+int panel_lightup(struct intel_dp *dp, unsigned int init_fb)
-		unsigned int pgfx, unsigned int init_fb)
 {
-	int must_cycle_power = 0;
-	struct intel_dp adp, *dp = &adp;
 	int i;
 	int edid_ok;
 	int pixels = FRAME_BUFFER_BYTES/64;
 
 	gtt_write(PCH_PP_CONTROL,0xabcd000f);
 	delay(1);
-	mmio = (void *)pmmio;
-	physbase = pphysbase;
-	graphics = pgfx;
-	printk(BIOS_SPEW,
-	       "i915lightup: graphics %p mmio %p"
-	       "physbase %08x\n",
-	       (void *)graphics, mmio, physbase);
 
 	void runio(struct intel_dp *dp);
 	/* hard codes -- stuff you can only know from the mainboard */
@@ -240,11 +225,12 @@ int i915lightup(unsigned int pphysbase, unsigned int pmmio,
 	   2. Developer/Recovery mode: Set up a tasteful color
 	      so people know we are alive. */
         if (init_fb || show_test) {
-                set_translation_table(0, FRAME_BUFFER_PAGES, physbase, 4096);
+                set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase,
-		memset((void *)graphics, 0x55, FRAME_BUFFER_PAGES*4096);
+					4096);
+		memset((void *)dp->graphics, 0x55, FRAME_BUFFER_PAGES*4096);
         } else {
-		set_translation_table(0, FRAME_BUFFER_PAGES, physbase, 0);
+		set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 0);
-                memset((void*)graphics, 0, 4096);
+                memset((void*)dp->graphics, 0, 4096);
         }
 
 	dp->address = 0x50;
@@ -279,13 +265,14 @@ int i915lightup(unsigned int pphysbase, unsigned int pmmio,
 	printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.ha, dp->edid.va);
 	test_gfx(dp);
 
-	set_vbe_mode_info_valid(&dp->edid, graphics);
+	set_vbe_mode_info_valid(&dp->edid, (uintptr_t)dp->graphics);
 	i915_init_done = 1;
 	return 1;
 
 fail:
 	printk(BIOS_SPEW, "Graphics could not be started;");
-	if (0 && must_cycle_power){
+	/* unclear we will *ever* want to do this. */
+	if (0){
 		printk(BIOS_SPEW, "Turn off power and wait ...");
 		gtt_write(PCH_PP_CONTROL,0xabcd0000);
 		udelay(600000);

src/mainboard/google/peppy/i915io.c

@@ -60,7 +60,7 @@ void runio(struct intel_dp *dp,  int verbose)
 	mainboard_set_port_clk_dp(dp);
 
 	gtt_write(DSPSTRIDE(dp->plane),dp->stride);
-        gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_RGBX888);
+        gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_BGRX888);
 
 	gtt_write(DEIIR,0x00000080);
 	intel_dp_wait_reg(DEIIR, 0x00000000);
@@ -132,7 +132,7 @@ void runio(struct intel_dp *dp,  int verbose)
 	intel_dp_wait_reg(DEIIR, 0x00000000);
 
 	gtt_write(DSPSTRIDE(dp->plane),dp->stride);
-	gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_RGBX888);
+	gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
 
 	gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | EDP_BLC_ENABLE | PANEL_POWER_ON);
 

src/mainboard/google/slippy/Kconfig

@@ -18,8 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select MAINBOARD_HAS_CHROMEOS
 	select EXTERNAL_MRC_BLOB
 	select MONOTONIC_TIMER_MSR
-	select MAINBOARD_HAS_NATIVE_VGA_INIT
-	select MAINBOARD_DO_NATIVE_VGA_INIT
 	select INTEL_DP
 	select INTEL_DDI
 	select INTEL_INT15

src/northbridge/intel/haswell/gma.c

@@ -426,21 +426,18 @@ static void gma_pm_init_post_vbios(struct device *dev)
 
 static void gma_func0_init(struct device *dev)
 {
+#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
+	struct northbridge_intel_haswell_config *conf = dev->chip_info;
+	struct intel_dp dp;
+#endif
+
 	int lightup_ok = 0;
 	u32 reg32;
-	u32 graphics_base; //, graphics_size;
 	/* IGD needs to be Bus Master */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
 	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
 	pci_write_config32(dev, PCI_COMMAND, reg32);
 
-
-	/* the BAR for graphics space is a well known number for
-	 * sandy and ivy. And the resource code renumbers it.
-	 * So it's almost like having two hardcodes.
-	 */
-	graphics_base = dev->resource_list[1].base;
-
 	/* Init graphics power management */
 	gma_pm_init_pre_vbios(dev);
 
@@ -449,17 +446,25 @@ static void gma_func0_init(struct device *dev)
 
 #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
 	printk(BIOS_SPEW, "NATIVE graphics, run native enable\n");
-	u32 mmiobase, physbase;
 	/* Default set to 1 since it might be required for
 	   stuff like seabios */
 	unsigned int init_fb = 1;
-	mmiobase = dev->resource_list[0].base;
+
-	physbase = pci_read_config32(dev, 0x5c) & ~0xf;
+	/* the BAR for graphics space is a well known number for
+	 * sandy and ivy. And the resource code renumbers it.
+	 * So it's almost like having two hardcodes.
+	 */
+	dp.graphics = (void *)((uintptr_t)dev->resource_list[1].base);
+	dp.physbase = pci_read_config32(dev, 0x5c) & ~0xf;
+	dp.panel_power_down_delay = conf->gpu_panel_power_down_delay;
+	dp.panel_power_up_delay = conf->gpu_panel_power_up_delay;
+	dp.panel_power_cycle_delay = conf->gpu_panel_power_cycle_delay;
+
+	dp.physbase = pci_read_config32(dev, 0x5c) & ~0xf;
 #ifdef CONFIG_CHROMEOS
 	init_fb = developer_mode_enabled() || recovery_mode_enabled();
 #endif
-	lightup_ok = i915lightup(physbase, mmiobase, graphics_base, init_fb);
+	lightup_ok = panel_lightup(&dp, init_fb);
-	if (lightup_ok)
 		gfx_set_init_done(1);
 #endif
 	if (! lightup_ok) {