Haswell/falco/peppy/slippy: continue to clean up FUI.
As a first step towards removing hardcodes from the FUI support, change the haswell call to i915_lightup to panel_lightup, and pass the intel_dp * as a parameter. Get rid of the scalar arguments and make them part of intel_dp. Get rid of file-scope variables and use the ones in the intel_dp struct. In falco, use functions that peppy uses. Drop slippy support for FUI, it's a dead board; if this is ok I'll remove the files next. And, incidentally, fix the broken RGBX constant and change it to BGRX. Change-Id: I46ef5a9ed8433382d042066ee3542af04cfc319a Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/174932 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 1e1ed410b445c8e2b7411e163d9d6f61499dc3f6) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6833 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
This commit is contained in:
Ronald G. Minnich
Isaac Christensen
parent
2120e0e200
commit
3a75e5e864
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@ -175,6 +175,12 @@ struct intel_dp {
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struct intel_dp_m_n m_n;
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u32 flags;
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u32 transcoder;
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/* parameters computed by the early startup, to be used
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* in the GMA code.
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*/
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u8 *graphics;
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/* physical address, not to be used directly. */
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u64 physbase;
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};
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/* we may yet need these. */
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@ -278,6 +284,7 @@ u32 gtt_read(u32 reg);
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int i915lightup(unsigned int physbase, unsigned int mmio,
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unsigned int gfx, unsigned int init_fb);
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int panel_lightup(struct intel_dp *dp, unsigned int init_fb);
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/* display.c */
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void compute_display_params(struct intel_dp *dp);
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@ -43,6 +43,7 @@
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#include <cpu/x86/msr.h>
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#include <edid.h>
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#include <drivers/intel/gma/i915.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include "mainboard.h"
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/*
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@ -86,52 +87,6 @@
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*/
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#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
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static unsigned int *mmio;
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static unsigned int graphics;
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static unsigned int physbase;
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void ug1(int);
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void ug2(int);
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void ug22(int);
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void ug3(int);
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/* GTT is the Global Translation Table for the graphics pipeline.
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* It is used to translate graphics addresses to physical
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* memory addresses. As in the CPU, GTTs map 4K pages.
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* The setgtt function adds a further bit of flexibility:
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* it allows you to set a range (the first two parameters) to point
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* to a physical address (third parameter);the physical address is
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* incremented by a count (fourth parameter) for each GTT in the
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* range.
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* Why do it this way? For ultrafast startup,
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* we can point all the GTT entries to point to one page,
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* and set that page to 0s:
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* memset(physbase, 0, 4096);
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* setgtt(0, 4250, physbase, 0);
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* this takes about 2 ms, and is a win because zeroing
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* the page takes a up to 200 ms.
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* This call sets the GTT to point to a linear range of pages
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* starting at physbase.
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*/
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#define GTT_PTE_BASE (2 << 20)
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static void
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setgtt(int start, int end, unsigned long base, int inc)
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{
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int i;
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for(i = start; i < end; i++){
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u32 word = base + i*inc;
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/* note: we've confirmed by checking
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* the values that mrc does no
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* useful setup before we run this.
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*/
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gtt_write(GTT_PTE_BASE + i * 4, word|1);
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gtt_read(GTT_PTE_BASE + i * 4);
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}
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}
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static int i915_init_done = 0;
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/* fill the palette. */
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@ -145,75 +100,6 @@ static void palette(void)
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}
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}
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void dp_init_dim_regs(struct intel_dp *dp);
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void dp_init_dim_regs(struct intel_dp *dp)
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{
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struct edid *edid = &(dp->edid);
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dp->bytes_per_pixel = edid->framebuffer_bits_per_pixel / 8;
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dp->stride = edid->bytes_per_line;
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dp->htotal = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
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dp->hblank = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
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dp->hsync = (edid->ha + edid->hso - 1) |
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((edid->ha + edid->hso + edid->hspw - 1) << 16);
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dp->vtotal = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
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dp->vblank = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
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dp->vsync = (edid->va + edid->vso - 1) |
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((edid->va + edid->vso + edid->vspw - 1) << 16);
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/* PIPEASRC is wid-1 x ht-1 */
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dp->pipesrc = (edid->ha-1)<<16 | (edid->va-1);
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dp->pfa_pos = 0;
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dp->pfa_ctl = 0x80800000;
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dp->pfa_sz = (edid->ha << 16) | (edid->va);
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dp->flags = intel_ddi_calc_transcoder_flags(3 * 6, /* bits per color is 6 */
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dp->port,
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dp->pipe,
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dp->type,
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dp->lane_count,
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dp->pfa_sz,
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dp->edid.phsync == '+'?1:0,
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dp->edid.pvsync == '+'?1:0);
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dp->transcoder = intel_ddi_get_transcoder(dp->port,
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dp->pipe);
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intel_dp_compute_m_n(dp->pipe_bits_per_pixel,
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dp->lane_count,
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dp->edid.pixel_clock,
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dp->edid.link_clock,
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&dp->m_n);
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printk(BIOS_SPEW, "dp->stride = 0x%08x\n",dp->stride);
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printk(BIOS_SPEW, "dp->htotal = 0x%08x\n", dp->htotal);
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printk(BIOS_SPEW, "dp->hblank = 0x%08x\n", dp->hblank);
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printk(BIOS_SPEW, "dp->hsync = 0x%08x\n", dp->hsync);
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printk(BIOS_SPEW, "dp->vtotal = 0x%08x\n", dp->vtotal);
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printk(BIOS_SPEW, "dp->vblank = 0x%08x\n", dp->vblank);
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printk(BIOS_SPEW, "dp->vsync = 0x%08x\n", dp->vsync);
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printk(BIOS_SPEW, "dp->pipesrc = 0x%08x\n", dp->pipesrc);
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printk(BIOS_SPEW, "dp->pfa_pos = 0x%08x\n", dp->pfa_pos);
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printk(BIOS_SPEW, "dp->pfa_ctl = 0x%08x\n", dp->pfa_ctl);
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printk(BIOS_SPEW, "dp->pfa_sz = 0x%08x\n", dp->pfa_sz);
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printk(BIOS_SPEW, "dp->link_m = 0x%08x\n", dp->m_n.link_m);
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printk(BIOS_SPEW, "dp->link_n = 0x%08x\n", dp->m_n.link_n);
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printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m);
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printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", dp->m_n.gmch_m);
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printk(BIOS_SPEW, "0x6f034 = 0x%08x\n", dp->m_n.gmch_n);
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printk(BIOS_SPEW, "dp->flags = 0x%08x\n", dp->flags);
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}
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void mainboard_train_link(struct intel_dp *intel_dp)
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{
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u8 read_val;
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@ -289,25 +175,14 @@ void mainboard_set_port_clk_dp(struct intel_dp *intel_dp)
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gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel);
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}
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int i915lightup(unsigned int pphysbase, unsigned int pmmio,
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unsigned int pgfx, unsigned int init_fb)
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int panel_lightup(struct intel_dp *dp, unsigned int init_fb)
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{
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int must_cycle_power = 0;
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struct intel_dp adp, *dp = &adp;
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int i;
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int edid_ok;
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int pixels = FRAME_BUFFER_BYTES/64;
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mmio = (void *)pmmio;
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physbase = pphysbase;
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graphics = pgfx;
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printk(BIOS_SPEW,
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"i915lightup: graphics %p mmio %p"
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"physbase %08x\n",
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(void *)graphics, mmio, physbase);
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void runio(struct intel_dp *dp);
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void runlinux(struct intel_dp *dp);
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dp->gen = 8; // This is gen 8 which we believe is Haswell
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dp->is_haswell = 1;
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dp->DP = 0x2;
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@ -332,11 +207,12 @@ int i915lightup(unsigned int pphysbase, unsigned int pmmio,
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all GTT entries point to the same page
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2. Developer/Recovery mode: We do not zero out all
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the pages pointed to by GTT in order to avoid wasting time */
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if (init_fb)
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setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
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else {
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setgtt(0, FRAME_BUFFER_PAGES, physbase, 0);
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memset((void*)graphics, 0, 4096);
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if (init_fb){
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set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 4096);
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memset((void *)dp->graphics, 0x55, FRAME_BUFFER_PAGES*4096);
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} else {
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set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 0);
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memset((void*)dp->graphics, 0, 4096);
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}
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dp->address = 0x50;
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@ -355,11 +231,7 @@ int i915lightup(unsigned int pphysbase, unsigned int pmmio,
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edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid);
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printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok);
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dp->edid.link_clock = intel_dp_bw_code_to_link_rate(dp->link_bw);
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printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n",dp->edid.pixel_clock, dp->edid.link_clock);
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dp_init_dim_regs(dp);
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compute_display_params(dp);
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intel_ddi_set_pipe_settings(dp);
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@ -372,18 +244,12 @@ int i915lightup(unsigned int pphysbase, unsigned int pmmio,
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test_gfx(dp);
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set_vbe_mode_info_valid(&dp->edid, graphics);
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set_vbe_mode_info_valid(&dp->edid, (uintptr_t)dp->graphics);
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i915_init_done = 1;
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return i915_init_done;
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fail:
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printk(BIOS_SPEW, "Graphics could not be started;");
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if (0 && must_cycle_power){
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printk(BIOS_SPEW, "Turn off power and wait ...");
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gtt_write(PCH_PP_CONTROL,0xabcd0000);
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udelay(600000);
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gtt_write(PCH_PP_CONTROL,0xabcd000f);
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}
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printk(BIOS_SPEW, "Returning.\n");
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return 0;
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}
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@ -28,12 +28,6 @@
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#include <arch/io.h>
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#include "mainboard.h"
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/* these variables will be removed when the proper support is finished in src/drivers/intel/gma/intel_dp.c */
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int index;
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u32 auxout;
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u8 auxin[20];
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u8 msg[32];
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/* this function will either be renamed or subsumed into ./gma.c:i915_lightup */
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void runio(struct intel_dp *dp);
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@ -72,7 +66,7 @@ void runio(struct intel_dp *dp)
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mainboard_set_port_clk_dp(dp);
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gtt_write(DSPSTRIDE(dp->plane),dp->stride);
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gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_RGBX888);
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gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_BGRX888);
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gtt_write(DEIIR,0x00000080);
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gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags);
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@ -125,7 +119,7 @@ void runio(struct intel_dp *dp)
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intel_dp_wait_reg(DEIIR, 0x00000000);
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gtt_write(DSPSTRIDE(dp->plane),dp->stride);
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gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_RGBX888);
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gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
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gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON);
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@ -0,0 +1,25 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __MAINBOARD_H_
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#define __MAINBOARD_H_
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void mainboard_train_link(struct intel_dp *intel_dp);
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void mainboard_set_port_clk_dp(struct intel_dp *intel_dp);
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#endif
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@ -374,7 +374,7 @@ int i915lightup(const struct northbridge_intel_sandybridge_config *info,
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(void *)graphics, FRAME_BUFFER_BYTES);
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memset((void *)graphics, 0, FRAME_BUFFER_BYTES);
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printk(BIOS_SPEW, "%ld microseconds\n", globalmicroseconds());
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set_vbe_mode_info_valid(&edid, graphics);
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set_vbe_mode_info_valid(&edid, (uintptr_t)graphics);
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i915_init_done = 1;
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return i915_init_done;
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}
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@ -87,9 +87,6 @@
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*/
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#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
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static unsigned int *mmio;
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static unsigned int graphics;
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static unsigned int physbase;
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static int i915_init_done = 0;
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@ -155,8 +152,6 @@ static void test_gfx(struct intel_dp *dp)
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green and blue. It is very useful to ensure all the initializations
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are made right. Thus, to be used only for testing, not otherwise
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*/
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printk(BIOS_SPEW, "TEST: graphics %p, va %d, ha %d, stride %d\n",
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(u32 *)graphics, dp->edid.va, dp->edid.ha, dp->stride);
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for (i = 0; i < (dp->edid.va - 4); i++) {
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u32 *l;
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@ -166,7 +161,7 @@ static void test_gfx(struct intel_dp *dp)
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if (j == (dp->edid.ha/2)) {
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tcolor = 0xff00;
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}
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l = (u32*)(graphics + i * dp->stride + j * sizeof(tcolor));
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l = (u32*)(dp->graphics + i * dp->stride + j * sizeof(tcolor));
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memcpy(l,&tcolor,sizeof(tcolor));
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}
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}
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@ -196,24 +191,14 @@ void mainboard_set_port_clk_dp(struct intel_dp *intel_dp)
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gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel);
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}
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int i915lightup(unsigned int pphysbase, unsigned int pmmio,
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unsigned int pgfx, unsigned int init_fb)
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int panel_lightup(struct intel_dp *dp, unsigned int init_fb)
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{
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int must_cycle_power = 0;
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struct intel_dp adp, *dp = &adp;
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int i;
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int edid_ok;
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int pixels = FRAME_BUFFER_BYTES/64;
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gtt_write(PCH_PP_CONTROL,0xabcd000f);
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delay(1);
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mmio = (void *)pmmio;
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physbase = pphysbase;
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graphics = pgfx;
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printk(BIOS_SPEW,
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"i915lightup: graphics %p mmio %p"
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"physbase %08x\n",
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(void *)graphics, mmio, physbase);
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void runio(struct intel_dp *dp);
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/* hard codes -- stuff you can only know from the mainboard */
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@ -240,11 +225,12 @@ int i915lightup(unsigned int pphysbase, unsigned int pmmio,
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2. Developer/Recovery mode: Set up a tasteful color
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so people know we are alive. */
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if (init_fb || show_test) {
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set_translation_table(0, FRAME_BUFFER_PAGES, physbase, 4096);
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memset((void *)graphics, 0x55, FRAME_BUFFER_PAGES*4096);
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set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase,
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4096);
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memset((void *)dp->graphics, 0x55, FRAME_BUFFER_PAGES*4096);
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} else {
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set_translation_table(0, FRAME_BUFFER_PAGES, physbase, 0);
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memset((void*)graphics, 0, 4096);
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set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 0);
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memset((void*)dp->graphics, 0, 4096);
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}
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dp->address = 0x50;
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@ -279,13 +265,14 @@ int i915lightup(unsigned int pphysbase, unsigned int pmmio,
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printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.ha, dp->edid.va);
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test_gfx(dp);
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set_vbe_mode_info_valid(&dp->edid, graphics);
|
||||
set_vbe_mode_info_valid(&dp->edid, (uintptr_t)dp->graphics);
|
||||
i915_init_done = 1;
|
||||
return 1;
|
||||
|
||||
fail:
|
||||
printk(BIOS_SPEW, "Graphics could not be started;");
|
||||
if (0 && must_cycle_power){
|
||||
/* unclear we will *ever* want to do this. */
|
||||
if (0){
|
||||
printk(BIOS_SPEW, "Turn off power and wait ...");
|
||||
gtt_write(PCH_PP_CONTROL,0xabcd0000);
|
||||
udelay(600000);
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ void runio(struct intel_dp *dp, int verbose)
|
|||
mainboard_set_port_clk_dp(dp);
|
||||
|
||||
gtt_write(DSPSTRIDE(dp->plane),dp->stride);
|
||||
gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_RGBX888);
|
||||
gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_BGRX888);
|
||||
|
||||
gtt_write(DEIIR,0x00000080);
|
||||
intel_dp_wait_reg(DEIIR, 0x00000000);
|
||||
|
|
@ -132,7 +132,7 @@ void runio(struct intel_dp *dp, int verbose)
|
|||
intel_dp_wait_reg(DEIIR, 0x00000000);
|
||||
|
||||
gtt_write(DSPSTRIDE(dp->plane),dp->stride);
|
||||
gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_RGBX888);
|
||||
gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
|
||||
|
||||
gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | EDP_BLC_ENABLE | PANEL_POWER_ON);
|
||||
|
||||
|
|
|
|||
|
|
@ -18,8 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
select MAINBOARD_HAS_CHROMEOS
|
||||
select EXTERNAL_MRC_BLOB
|
||||
select MONOTONIC_TIMER_MSR
|
||||
select MAINBOARD_HAS_NATIVE_VGA_INIT
|
||||
select MAINBOARD_DO_NATIVE_VGA_INIT
|
||||
select INTEL_DP
|
||||
select INTEL_DDI
|
||||
select INTEL_INT15
|
||||
|
|
|
|||
|
|
@ -426,21 +426,18 @@ static void gma_pm_init_post_vbios(struct device *dev)
|
|||
|
||||
static void gma_func0_init(struct device *dev)
|
||||
{
|
||||
#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
|
||||
struct northbridge_intel_haswell_config *conf = dev->chip_info;
|
||||
struct intel_dp dp;
|
||||
#endif
|
||||
|
||||
int lightup_ok = 0;
|
||||
u32 reg32;
|
||||
u32 graphics_base; //, graphics_size;
|
||||
/* IGD needs to be Bus Master */
|
||||
reg32 = pci_read_config32(dev, PCI_COMMAND);
|
||||
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
|
||||
pci_write_config32(dev, PCI_COMMAND, reg32);
|
||||
|
||||
|
||||
/* the BAR for graphics space is a well known number for
|
||||
* sandy and ivy. And the resource code renumbers it.
|
||||
* So it's almost like having two hardcodes.
|
||||
*/
|
||||
graphics_base = dev->resource_list[1].base;
|
||||
|
||||
/* Init graphics power management */
|
||||
gma_pm_init_pre_vbios(dev);
|
||||
|
||||
|
|
@ -449,17 +446,25 @@ static void gma_func0_init(struct device *dev)
|
|||
|
||||
#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
|
||||
printk(BIOS_SPEW, "NATIVE graphics, run native enable\n");
|
||||
u32 mmiobase, physbase;
|
||||
/* Default set to 1 since it might be required for
|
||||
stuff like seabios */
|
||||
unsigned int init_fb = 1;
|
||||
mmiobase = dev->resource_list[0].base;
|
||||
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
|
||||
|
||||
/* the BAR for graphics space is a well known number for
|
||||
* sandy and ivy. And the resource code renumbers it.
|
||||
* So it's almost like having two hardcodes.
|
||||
*/
|
||||
dp.graphics = (void *)((uintptr_t)dev->resource_list[1].base);
|
||||
dp.physbase = pci_read_config32(dev, 0x5c) & ~0xf;
|
||||
dp.panel_power_down_delay = conf->gpu_panel_power_down_delay;
|
||||
dp.panel_power_up_delay = conf->gpu_panel_power_up_delay;
|
||||
dp.panel_power_cycle_delay = conf->gpu_panel_power_cycle_delay;
|
||||
|
||||
dp.physbase = pci_read_config32(dev, 0x5c) & ~0xf;
|
||||
#ifdef CONFIG_CHROMEOS
|
||||
init_fb = developer_mode_enabled() || recovery_mode_enabled();
|
||||
#endif
|
||||
lightup_ok = i915lightup(physbase, mmiobase, graphics_base, init_fb);
|
||||
if (lightup_ok)
|
||||
lightup_ok = panel_lightup(&dp, init_fb);
|
||||
gfx_set_init_done(1);
|
||||
#endif
|
||||
if (! lightup_ok) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue