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mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP 

TEST=Able to pass MRC training on DDR4/5 SKUs

Change-Id: I38fcb17a1be5a8544a17cef8255631b6abef0741
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik 2020-11-27 00:20:18 +05:30
parent f79f00991c
commit 3a873b5c9a
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/intel/adlrvp/memory.c
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@ -12,7 +12,7 @@ static const struct mb_cfg ddr4_mem_config = {
/* Baseboard Rcomp target values */ /* Baseboard Rcomp target values */
.rcomp_targets = {40, 30, 33, 33, 30}, .rcomp_targets = {40, 30, 33, 33, 30},
.dq_pins_interleaved = true, .dq_pins_interleaved = false,
.ect = true, /* Early Command Training */ .ect = true, /* Early Command Training */
@ -61,7 +61,7 @@ static const struct mb_cfg ddr5_mem_config = {
/* Baseboard Rcomp target values */ /* Baseboard Rcomp target values */
.rcomp_targets = {50, 30, 30, 30, 27}, .rcomp_targets = {50, 30, 30, 30, 27},
.dq_pins_interleaved = true, .dq_pins_interleaved = false,
.ect = true, /* Early Command Training */ .ect = true, /* Early Command Training */