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src/northbridge: Remove unnecessary space after casts 

Change-Id: If6c1a17d15e24ecdc56b0cc9cb7e7dc7d6e6936b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69813
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes Haouas 2022-11-18 15:11:02 +01:00 committed by Felix Held
parent ab6d94430e
commit 3a9980767e
12 changed files with 47 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/northbridge/amd/pi/00730F01/acpi_tables.c
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@ -13,7 +13,7 @@ unsigned long acpi_fill_madt(unsigned long current)
IO_APIC_ADDR, 0);
/* TODO: Remove the hardcode */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS + 1,
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS + 1,
0xFEC20000, 24);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)

2
src/northbridge/intel/gm45/acpi.c
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@ -63,7 +63,7 @@ unsigned long northbridge_write_acpi_tables(const struct device *device,
current = start;
printk(BIOS_DEBUG, "ACPI: * DMAR\n");
dmar = (acpi_dmar_t *) current;
dmar = (acpi_dmar_t *)current;
acpi_create_dmar(dmar, 0, acpi_fill_dmar);
current += dmar->header.length;
current = acpi_align_current(current);

2
src/northbridge/intel/haswell/report_platform.c
View File

@ -22,7 +22,7 @@ static void report_cpu_info(void)
if (cpuidr.eax < 0x80000004) {
strcpy(cpu_string, "Platform info not available");
} else {
u32 *p = (u32*) cpu_string;
u32 *p = (u32 *)cpu_string;
for (i = 2; i <= 4; i++) {
cpuidr = cpuid(index + i);
*p++ = cpuidr.eax;

2
src/northbridge/intel/i440bx/raminit.c
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@ -358,7 +358,7 @@ static void do_ram_command(u32 command)
/* Configure the RAM command. */
reg16 = pci_read_config16(NB, SDRAMC);
reg16 &= 0xff1f; /* Clear bits 7-5. */
reg16 |= (u16) (command << 5); /* Write command into bits 7-5. */
reg16 |= (u16)(command << 5); /* Write command into bits 7-5. */
pci_write_config16(NB, SDRAMC, reg16);
/*

4
src/northbridge/intel/ironlake/gma.c
View File

@ -179,8 +179,8 @@ static void gma_read_resources(struct device *dev)
res->flags |= IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_ASSIGNED;
pci_write_config32(dev, PCI_BASE_ADDRESS_2, 0xd0000001);
pci_write_config32(dev, PCI_BASE_ADDRESS_2 + 4, 0);
res->base = (resource_t) 0xd0000000;
res->size = (resource_t) 0x10000000;
res->base = (resource_t)0xd0000000;
res->size = (resource_t)0x10000000;
}
static void gma_generate_ssdt(const struct device *device)

4
src/northbridge/intel/ironlake/northbridge.c
View File

@ -48,8 +48,8 @@ static void add_fixed_resources(struct device *dev, int index)
0xff800000-0xffffffff ROM. */
resource = new_resource(dev, index++);
resource->base = (resource_t) HPET_BASE_ADDRESS;
resource->size = (resource_t) 0x00100000;
resource->base = (resource_t)HPET_BASE_ADDRESS;
resource->size = (resource_t)0x00100000;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;

10
src/northbridge/intel/ironlake/quickpath.c
View File

@ -98,9 +98,9 @@ compute_frequence_ratios(struct raminfo *info, u16 freq1, u16 freq2,
(freq1_reduced - freq2_reduced)) / freq2_reduced;
result->freq4_to_2_remainder =
-(char)((freq1_reduced - freq2_reduced) +
((u8) freq4 -
((u8)freq4 -
(freq1_reduced -
freq2_reduced)) % (u8) freq2_reduced);
freq2_reduced)) % (u8)freq2_reduced);
} else {
if (freq2_reduced > freq1_reduced) {
result->freq4_to_max_remainder =
@ -275,11 +275,11 @@ set_2d5x_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2,
+ vv.freq_min_reduced - 1, vv.freq_max_reduced) - 1;
u32 y =
(u8) ((vv.freq_max_reduced - vv.freq_min_reduced) +
(u8)((vv.freq_max_reduced - vv.freq_min_reduced) +
vv.freq_max_reduced * multiplier)
| (vv.
freqs_reversed << 8) | ((u8) (vv.freq_min_reduced *
multiplier) << 16) | ((u8) (vv.
freqs_reversed << 8) | ((u8)(vv.freq_min_reduced *
multiplier) << 16) | ((u8)(vv.
freq_min_reduced
*
multiplier)

2
src/northbridge/intel/ironlake/raminit.c
View File

@ -1651,7 +1651,7 @@ static u8 check_testing(struct raminfo *info, u8 total_rank, int flip)
u32 curroffset =
comp3 * 8 * 60 + 2 * comp1 + 8 * comp2;
read128((total_rank << 28) | (curroffset << 3),
(u64 *) re);
(u64 *)re);
failxor[0] |=
get_etalon2(flip, curroffset) ^ re[0];
failxor[1] |=

4
src/northbridge/intel/pineview/northbridge.c
View File

@ -26,8 +26,8 @@ static void add_fixed_resources(struct device *dev, int index)
struct resource *resource;
resource = new_resource(dev, index++);
resource->base = (resource_t) HPET_BASE_ADDRESS;
resource->size = (resource_t) 0x00100000;
resource->base = (resource_t)HPET_BASE_ADDRESS;
resource->size = (resource_t)0x00100000;
resource->flags = IORESOURCE_MEM
| IORESOURCE_RESERVE
| IORESOURCE_FIXED

52
src/northbridge/intel/pineview/raminit.c
View File

@ -526,7 +526,7 @@ static void sdram_detect_ram_speed(struct sysinfo *s)
s->pioffset = 1;
} else {
PRINTK_DEBUG("MCH set to unknown (%02x)\n",
(uint8_t) s->selected_timings.mem_clock & 0xff);
(uint8_t)s->selected_timings.mem_clock & 0xff);
}
}
@ -723,7 +723,7 @@ static void sdram_timings(struct sysinfo *s)
if (wl > 2) {
flag = 1;
}
reg16 = (u8) (wl - 1 - flag);
reg16 = (u8)(wl - 1 - flag);
reg16 |= reg16 << 4;
reg16 |= flag << 8;
mchbar_clrsetbits16(C0WRDATACTRL, 0x1ff, reg16);
@ -794,11 +794,11 @@ static void sdram_timings(struct sysinfo *s)
reg32 = (2 << 29) | (1 << 28) | (1 << 23);
mchbar_clrsetbits32(WRWMCONFIG, 0xffb << 20, reg32);
reg8 = (u8) ((mchbar_read16(C0CYCTRKACT) & 0xe000) >> 13);
reg8 |= (u8) ((mchbar_read16(C0CYCTRKACT + 2) & 1) << 3);
reg8 = (u8)((mchbar_read16(C0CYCTRKACT) & 0xe000) >> 13);
reg8 |= (u8)((mchbar_read16(C0CYCTRKACT + 2) & 1) << 3);
mchbar_clrsetbits8(BYPACTSF, 0xf << 4, reg8 << 4);
reg8 = (u8) ((mchbar_read32(C0CYCTRKRD) & 0x000f0000) >> 17);
reg8 = (u8)((mchbar_read32(C0CYCTRKRD) & 0x000f0000) >> 17);
mchbar_clrsetbits8(BYPACTSF, 0xf, reg8);
/* FIXME: Why not clear everything at once? */
@ -875,12 +875,12 @@ static void sdram_p_ctrl(const struct pllparam *pll, u8 f, u8 i)
u32 reg32;
/* CTRL0 and CTRL1 */
reg32 = ((u32) pll->dbsel[f][i]) << 20;
reg32 |= ((u32) pll->dben[f][i]) << 21;
reg32 |= ((u32) pll->dbsel[f][i]) << 22;
reg32 |= ((u32) pll->dben[f][i]) << 23;
reg32 |= ((u32) pll->clkdelay[f][i]) << 24;
reg32 |= ((u32) pll->clkdelay[f][i]) << 27;
reg32 = ((u32)pll->dbsel[f][i]) << 20;
reg32 |= ((u32)pll->dben[f][i]) << 21;
reg32 |= ((u32)pll->dbsel[f][i]) << 22;
reg32 |= ((u32)pll->dben[f][i]) << 23;
reg32 |= ((u32)pll->clkdelay[f][i]) << 24;
reg32 |= ((u32)pll->clkdelay[f][i]) << 27;
mchbar_clrsetbits32(C0CTLTX2, 0x01bf0000, reg32);
reg8 = pll->pi[f][i];
@ -888,12 +888,12 @@ static void sdram_p_ctrl(const struct pllparam *pll, u8 f, u8 i)
mchbar_clrsetbits8(C0TXCTL1DLL, 0x3f, reg8);
/* CTRL2 and CTRL3 */
reg32 = ((u32) pll->dbsel[f][i]) << 12;
reg32 |= ((u32) pll->dben[f][i]) << 13;
reg32 |= ((u32) pll->dbsel[f][i]) << 8;
reg32 |= ((u32) pll->dben[f][i]) << 9;
reg32 |= ((u32) pll->clkdelay[f][i]) << 14;
reg32 |= ((u32) pll->clkdelay[f][i]) << 10;
reg32 = ((u32)pll->dbsel[f][i]) << 12;
reg32 |= ((u32)pll->dben[f][i]) << 13;
reg32 |= ((u32)pll->dbsel[f][i]) << 8;
reg32 |= ((u32)pll->dben[f][i]) << 9;
reg32 |= ((u32)pll->clkdelay[f][i]) << 14;
reg32 |= ((u32)pll->clkdelay[f][i]) << 10;
mchbar_clrsetbits32(C0CMDTX2, 0xff << 8, reg32);
reg8 = pll->pi[f][i];
@ -912,12 +912,12 @@ static void sdram_p_dqs(struct pllparam *pll, u8 f, u8 clk)
rank = j % 4;
dqs = j / 4;
reg32 |= ((u32) pll->dben[f][clk]) << (dqs + 9);
reg32 |= ((u32) pll->dbsel[f][clk]) << dqs;
reg32 |= ((u32)pll->dben[f][clk]) << (dqs + 9);
reg32 |= ((u32)pll->dbsel[f][clk]) << dqs;
mchbar_clrsetbits32(C0DQSRyTX1(rank), 1 << (dqs + 9) | 1 << dqs, reg32);
reg32 = ((u32) pll->clkdelay[f][clk]) << ((dqs * 2) + 16);
reg32 = ((u32)pll->clkdelay[f][clk]) << ((dqs * 2) + 16);
mchbar_clrsetbits32(C0DQSDQRyTX3(rank), 1 << (dqs * 2 + 17) | 1 << (dqs * 2 + 16),
reg32);
@ -936,12 +936,12 @@ static void sdram_p_dq(struct pllparam *pll, u8 f, u8 clk)
rank = j % 4;
dq = j / 4;
reg32 |= ((u32) pll->dben[f][clk]) << (dq + 9);
reg32 |= ((u32) pll->dbsel[f][clk]) << dq;
reg32 |= ((u32)pll->dben[f][clk]) << (dq + 9);
reg32 |= ((u32)pll->dbsel[f][clk]) << dq;
mchbar_clrsetbits32(C0DQRyTX1(rank), 1 << (dq + 9) | 1 << dq, reg32);
reg32 = ((u32) pll->clkdelay[f][clk]) << (dq*2);
reg32 = ((u32)pll->clkdelay[f][clk]) << (dq*2);
mchbar_clrsetbits32(C0DQSDQRyTX3(rank), 1 << (dq * 2 + 1) | 1 << (dq * 2), reg32);
reg8 = pll->pi[f][clk];
@ -1414,8 +1414,8 @@ static void sdram_rcomp(struct sysinfo *s)
;
reg32 = mchbar_read32(XCOMP);
rcompp = (u8) ((reg32 & ~(1 << 31)) >> 24);
rcompn = (u8) ((reg32 & ~(0xff800000)) >> 16);
rcompp = (u8)((reg32 & ~(1 << 31)) >> 24);
rcompn = (u8)((reg32 & ~(0xff800000)) >> 16);
FOR_EACH_RCOMP_GROUP(i) {
srup = (mchbar_read8(C0RCOMPCTRLx(i) + 1) & 0xc0) >> 6;
@ -2134,7 +2134,7 @@ static void sdram_enhancedmode(struct sysinfo *s)
FOR_EACH_POPULATED_RANK(s->dimms, ch, r) {
nranks++;
dra = (u8) ((mchbar_read32(C0DRA01) >> (8 * r)) & 0x7f);
dra = (u8)((mchbar_read32(C0DRA01) >> (8 * r)) & 0x7f);
curranksize = drbtab[dra];
if (maxranksize == 0) {
maxranksize = curranksize;

6
src/northbridge/intel/sandybridge/raminit_common.c
View File

@ -693,9 +693,9 @@ static u32 make_mr0(ramctr_timing *ctrl, u8 rank)
/* Convert CAS to MCH register friendly */
if (ctrl->CAS < 12) {
mch_cas = (u16) ((ctrl->CAS - 4) << 1);
mch_cas = (u16)((ctrl->CAS - 4) << 1);
} else {
mch_cas = (u16) (ctrl->CAS - 12);
mch_cas = (u16)(ctrl->CAS - 12);
mch_cas = ((mch_cas << 1) | 0x1);
}
@ -1732,7 +1732,7 @@ static void train_write_flyby(ramctr_timing *ctrl)
FOR_ALL_LANES {
u64 res = mchbar_read32(lane_base[lane] + GDCRTRAININGRESULT1(channel));
res |= ((u64) mchbar_read32(lane_base[lane] +
res |= ((u64)mchbar_read32(lane_base[lane] +
GDCRTRAININGRESULT2(channel))) << 32;
old = ctrl->timings[channel][slotrank].lanes[lane].tx_dqs;

4
src/northbridge/intel/sandybridge/raminit_native.c
View File

@ -555,7 +555,7 @@ static void dram_freq(ramctr_timing *ctrl)
* Exit early to prevent a system hang.
*/
reg1 = mchbar_read32(MC_BIOS_DATA);
val2 = (u8) reg1;
val2 = (u8)reg1;
if (val2)
return;
@ -577,7 +577,7 @@ static void dram_freq(ramctr_timing *ctrl)
/* Step 3 - Verify lock frequency */
reg1 = mchbar_read32(MC_BIOS_DATA);
val2 = (u8) reg1;
val2 = (u8)reg1;
if (val2 >= ctrl->FRQ) {
printk(BIOS_DEBUG, "MPLL frequency is set at : %d MHz\n",
(1000 << 8) / ctrl->tCK);