Add support to run SMM handler in TSEG instead of ASEG
Traditionally coreboot's SMM handler runs in ASEG (0xa0000), "behind" the graphics memory. This approach has two issues: - It limits the possible size of the SMM handler (and the number of CPUs supported in a system) - It's not considered a supported path anymore in newer CPUs. Change-Id: I9f2877e46873ab2ea8f1157ead4bc644a50be19e Signed-off-by: Duncan Laurie <dlaurie@google.com> Acked-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/842 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
This commit is contained in:
Stefan Reinauer
Peter Stuge
parent
6efbebdb58
commit
3aa067f595
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@ -62,6 +62,11 @@ endif
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smm-c-ccopts:=-D__SMM__
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smm-S-ccopts:=-D__SMM__
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# SMM TSEG base is dynamic
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ifeq ($(CONFIG_SMM_TSEG),y)
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smm-c-ccopts += -fpic
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endif
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ramstage-c-deps:=$$(OPTION_TABLE_H)
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romstage-c-deps:=$$(OPTION_TABLE_H)
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@ -6,6 +6,7 @@
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#include <string.h>
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#include <div64.h>
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#include <console/console.h>
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#include <console/vtxprintf.h>
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/* haha, don't need ctype.c */
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@ -115,6 +116,11 @@ int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args
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int count;
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#if defined(__SMM__) && CONFIG_SMM_TSEG
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/* Fix pointer in TSEG */
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tx_byte = console_tx_byte;
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#endif
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for (count=0; *fmt ; ++fmt) {
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if (*fmt != '%') {
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tx_byte(*fmt), count++;
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@ -22,15 +22,25 @@ ifeq ($(CONFIG_HAVE_SMI_HANDLER),y)
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ramstage-srcs += $(obj)/cpu/x86/smm/smm_wrap
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endif
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# Use TSEG specific entry point and linker script
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ifeq ($(CONFIG_SMM_TSEG),y)
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smm-y += smmhandler_tseg.S
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SMM_LDFLAGS := $(LDFLAGS) -pie
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SMM_LDSCRIPT := smm_tseg.ld
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else
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smm-y += smmhandler.S
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SMM_LDFLAGS := $(LDFLAGFS)
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SMM_LDSCRIPT := smm.ld
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endif
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smm-y += smihandler.c
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smm-y += smiutil.c
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$(obj)/cpu/x86/smm/smm.o: $$(smm-objs)
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$(CC) $(LDFLAGS) -nostdlib -r -o $@ $^
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$(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld $(obj)/ldoptions
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$(CC) $(LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
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$(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/ldoptions
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$(CC) $(SMM_LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/cpu/x86/smm/smm.o
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$(NM) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map
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$(OBJCOPY) -O binary $(obj)/cpu/x86/smm/smm.elf $(obj)/cpu/x86/smm/smm
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@ -25,10 +25,11 @@
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#include <cpu/x86/cache.h>
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#include <cpu/x86/smm.h>
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#if !CONFIG_SMM_TSEG /* TSEG handler locks in assembly */
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typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore;
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/* SMI multiprocessing semaphore */
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static volatile smi_semaphore smi_handler_status __attribute__ ((aligned (4))) = SMI_UNLOCKED;
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static volatile smi_semaphore smi_handler_status __attribute__ ((aligned (4))) = SMI_UNLOCKED;
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static int smi_obtain_lock(void)
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{
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@ -56,6 +57,7 @@ void smi_release_lock(void)
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: "eax"
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);
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}
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#endif
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#define LAPIC_ID 0xfee00020
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static inline __attribute__((always_inline)) unsigned long nodeid(void)
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@ -116,6 +118,7 @@ void smi_handler(u32 smm_revision)
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unsigned int node;
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smm_state_save_area_t state_save;
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#if !CONFIG_SMM_TSEG
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/* Are we ok to execute the handler? */
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if (!smi_obtain_lock()) {
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/* For security reasons we don't release the other CPUs
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@ -128,6 +131,7 @@ void smi_handler(u32 smm_revision)
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}
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return;
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}
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#endif
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smi_backup_pci_address();
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@ -145,6 +149,7 @@ void smi_handler(u32 smm_revision)
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(0xa8000 + 0x7e00 - (node * 0x400));
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break;
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case 0x00030100:
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case 0x00030101: /* SandyBridge */
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state_save.type = EM64T;
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state_save.em64t_state_save = (em64t_smm_state_save_area_t *)
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(0xa8000 + 0x7d00 - (node * 0x400));
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@ -173,7 +178,9 @@ void smi_handler(u32 smm_revision)
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smi_restore_pci_address();
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#if !CONFIG_SMM_TSEG
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smi_release_lock();
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#endif
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/* De-assert SMI# signal to allow another SMI */
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smi_set_eos();
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@ -0,0 +1,58 @@
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/* Maximum number of CPUs/cores */
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CPUS = 16;
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SECTIONS
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{
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/* This is the actual SMM handler.
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*
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* We just put code, rodata, data and bss all in a row.
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*/
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.handler (.): {
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/* Assembler stub */
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*(.handler)
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/* C code of the SMM handler */
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*(.text);
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*(.text.*);
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/* C read-only data of the SMM handler */
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. = ALIGN(16);
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*(.rodata)
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*(.rodata.*)
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*(.data.rel.ro.*)
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/* C read-write data of the SMM handler */
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. = ALIGN(4);
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*(.data)
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/* C uninitialized data of the SMM handler */
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. = ALIGN(4);
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*(.bss)
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*(.sbss)
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/* What is this? */
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*(COMMON)
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. = ALIGN(4);
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}
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/* We are using the TSEG interleaved to stuff the SMM handlers
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* for all CPU cores in there. The jump table redirects the execution
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* to the actual SMM handler
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*/
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. = 0x8000 - (( CPUS - 1) * 0x400);
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.jumptable : {
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*(.jumptable)
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}
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/* Data used in early SMM TSEG handler. */
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. = 0x8400;
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.earlydata : {
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*(.earlydata)
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}
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/DISCARD/ : {
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*(.comment)
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*(.note)
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*(.note.*)
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}
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}
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@ -0,0 +1,300 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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/*
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* +--------------------------------+ 0xffff
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* | Save State Map Node 0 |
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* | Save State Map Node 1 |
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* | Save State Map Node 2 |
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* | Save State Map Node 3 |
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* | ... |
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* +--------------------------------+ 0xf000
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* | |
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* | |
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* | EARLY DATA (lock, vectors) |
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* +--------------------------------+ 0x8400
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* | SMM Entry Node 0 (+ stack) |
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* +--------------------------------+ 0x8000
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* | SMM Entry Node 1 (+ stack) |
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* | SMM Entry Node 2 (+ stack) |
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* | SMM Entry Node 3 (+ stack) |
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* | ... |
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* +--------------------------------+ 0x7400
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* | |
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* | SMM Handler |
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* | |
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* +--------------------------------+ TSEG
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*
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*/
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#define LAPIC_ID 0xfee00020
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#define SMM_STACK_SIZE (0x400 - 0x10)
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/* Values for the xchg lock */
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#define SMI_LOCKED 0
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#define SMI_UNLOCKED 1
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#define __PRE_RAM__
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#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
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#else
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#error "Northbridge must define TSEG_BAR."
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#endif
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/* initially SMM is some sort of real mode. Let gcc know
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* how to treat the SMM handler stub
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*/
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.section ".handler", "a", @progbits
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.code16
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/**
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* SMM code to enable protected mode and jump to the
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* C-written function void smi_handler(u32 smm_revision)
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*
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* All the bad magic is not all that bad after all.
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*/
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smm_handler_start:
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movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */
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addr32 movl (%eax), %edx /* Save TSEG_BAR in %edx */
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andl $~1, %edx /* Remove lock bit */
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/* Obtain lock */
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movl %edx, %ebx
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addl $(smm_lock), %ebx
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movw $SMI_LOCKED, %ax
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addr32 xchg %ax, (%ebx)
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cmpw $SMI_UNLOCKED, %ax
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/* Proceed if we got the lock */
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je smm_check_prot_vector
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/* If we did not get the lock, wait for release */
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wait_for_unlock:
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addr32 movw (%ebx), %ax
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cmpw $SMI_LOCKED, %ax
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je wait_for_unlock
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rsm
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smm_check_prot_vector:
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/* See if we need to adjust protected vector */
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movl %edx, %eax
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addl $(smm_prot_vector), %eax
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addr32 movl (%eax), %ebx
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cmpl $(smm_prot_start), %ebx
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jne smm_check_gdt_vector
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/* Adjust vector with TSEG offset */
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addl %edx, %ebx
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addr32 movl %ebx, (%eax)
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smm_check_gdt_vector:
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/* See if we need to adjust GDT vector */
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movl %edx, %eax
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addl $(smm_gdt_vector + 2), %eax
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addr32 movl (%eax), %ebx
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cmpl $(smm_gdt - smm_handler_start), %ebx
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jne smm_load_gdt
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/* Adjust vector with TSEG offset */
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addl %edx, %ebx
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addr32 movl %ebx, (%eax)
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smm_load_gdt:
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movl $(smm_gdt_vector), %ebx
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addl %edx, %ebx /* TSEG base in %edx */
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data32 lgdt (%ebx)
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movl %cr0, %eax
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andl $0x1FFAFFD1, %eax /* CD,NW,PG,AM,WP,NE,TS,EM,MP = 0 */
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orl $0x1, %eax /* PE = 1 */
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movl %eax, %cr0
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/* Enable protected mode */
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movl $(smm_prot_vector), %eax
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addl %edx, %eax
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data32 ljmp *(%eax)
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.code32
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smm_prot_start:
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/* Use flat data segment */
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movw $0x10, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movw %ax, %gs
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/* Get this CPU's LAPIC ID */
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movl $LAPIC_ID, %esi
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movl (%esi), %ecx
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shr $24, %ecx
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/* calculate stack offset by multiplying the APIC ID
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* by 1024 (0x400), and save that offset in ebp.
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*/
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shl $10, %ecx
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movl %ecx, %ebp
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/* We put the stack for each core right above
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* its SMM entry point. Core 0 starts at SMM_BASE + 0x8000,
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* we spare 0x10 bytes for the jump to be sure.
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*/
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movl $0x8010, %eax /* core 0 address */
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addl %edx, %eax /* addjust for TSEG */
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subl %ecx, %eax /* subtract offset, see above */
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movl %eax, %ebx /* Save bottom of stack in ebx */
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/* clear stack */
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cld
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movl %eax, %edi
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movl $(SMM_STACK_SIZE >> 2), %ecx
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xorl %eax, %eax
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rep stosl
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/* set new stack */
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addl $SMM_STACK_SIZE, %ebx
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movl %ebx, %esp
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/* Get SMM revision */
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movl $0xfefc, %ebx /* core 0 address */
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addl %edx, %ebx /* addjust for TSEG */
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subl %ebp, %ebx /* subtract core X offset */
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movl (%ebx), %eax
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pushl %eax
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/* Call 32bit C handler */
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call smi_handler
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/* Release lock */
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movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */
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movl (%eax), %ebx /* Save TSEG_BAR in %ebx */
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andl $~1, %ebx /* Remove lock bit */
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addl $(smm_lock), %ebx
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movw $SMI_UNLOCKED, %ax
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xchg %ax, (%ebx)
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/* To return, just do rsm. It will "clean up" protected mode */
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rsm
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smm_gdt:
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/* The first GDT entry can not be used. Keep it zero */
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.long 0x00000000, 0x00000000
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/* gdt selector 0x08, flat code segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */
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/* gdt selector 0x10, flat data segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x93, 0xcf, 0x00
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smm_gdt_end:
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.section ".earlydata", "a", @progbits
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.code16
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.align 4, 0xff
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smm_lock:
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.word SMI_UNLOCKED
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.align 4, 0xff
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smm_prot_vector:
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.long smm_prot_start
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.short 8
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.align 4, 0xff
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smm_gdt_vector:
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.word smm_gdt_end - smm_gdt - 1
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.long smm_gdt - smm_handler_start
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.section ".jumptable", "a", @progbits
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/* This is the SMM jump table. All cores use the same SMM handler
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* for simplicity. But SMM Entry needs to be different due to the
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* save state area. The jump table makes sure all CPUs jump into the
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* real handler on SMM entry.
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*/
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/* This code currently supports up to 16 CPU cores. If more than 16 CPU cores
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* shall be used, below table has to be updated, as well as smm_tseg.ld
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*/
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/* When using TSEG do a relative jump and fix up the CS later since we
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* do not know what our TSEG base is yet.
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*/
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.code16
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jumptable:
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/* core 15 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 14 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 13 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 12 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 11 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 10 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 9 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 8 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 7 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 6 */
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jmp smm_handler_start
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.align 1024, 0x00
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/* core 5 */
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jmp smm_handler_start
|
||||
.align 1024, 0x00
|
||||
/* core 4 */
|
||||
jmp smm_handler_start
|
||||
.align 1024, 0x00
|
||||
/* core 3 */
|
||||
jmp smm_handler_start
|
||||
.align 1024, 0x00
|
||||
/* core 2 */
|
||||
jmp smm_handler_start
|
||||
.align 1024, 0x00
|
||||
/* core 1 */
|
||||
jmp smm_handler_start
|
||||
.align 1024, 0x00
|
||||
/* core 0 */
|
||||
jmp smm_handler_start
|
||||
.align 1024, 0x00
|
||||
|
|
@ -39,6 +39,12 @@
|
|||
#error "Southbridge needs SMM handler support."
|
||||
#endif
|
||||
|
||||
#if CONFIG_SMM_TSEG
|
||||
|
||||
#include <cpu/x86/mtrr.h>
|
||||
|
||||
#endif /* CONFIG_SMM_TSEG */
|
||||
|
||||
#define LAPIC_ID 0xfee00020
|
||||
|
||||
.global smm_relocation_start
|
||||
|
|
@ -100,6 +106,7 @@ smm_relocation_start:
|
|||
/* Check revision to see if AMD64 style SMM_BASE
|
||||
* Intel Core Solo/Duo: 0x30007
|
||||
* Intel Core2 Solo/Duo: 0x30100
|
||||
* Intel SandyBridge: 0x30101
|
||||
* AMD64: 0x3XX64
|
||||
* This check does not make much sense, unless someone ports
|
||||
* SMI handling to AMD64 CPUs.
|
||||
|
|
@ -127,11 +134,53 @@ smm_relocate:
|
|||
movl %ecx, %edx
|
||||
shl $10, %edx
|
||||
|
||||
#if CONFIG_SMM_TSEG
|
||||
movl $(TSEG_BAR), %ecx /* Get TSEG base from PCIE */
|
||||
addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */
|
||||
andl $~1, %eax /* Remove lock bit */
|
||||
#else
|
||||
movl $0xa0000, %eax
|
||||
#endif
|
||||
subl %edx, %eax /* subtract offset, see above */
|
||||
|
||||
addr32 movl %eax, (%ebx)
|
||||
|
||||
#if CONFIG_SMM_TSEG
|
||||
/* Check for SMRR capability in MTRRCAP[11] */
|
||||
movl $MTRRcap_MSR, %ecx
|
||||
rdmsr
|
||||
bt $11, %eax
|
||||
jnc skip_smrr
|
||||
|
||||
/* TSEG base */
|
||||
movl $(TSEG_BAR), %ecx /* Get TSEG base from PCIE */
|
||||
addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */
|
||||
andl $~1, %eax /* Remove lock bit */
|
||||
movl %eax, %ebx
|
||||
|
||||
/* Set SMRR base address. */
|
||||
movl $SMRRphysBase_MSR, %ecx
|
||||
orl $MTRR_TYPE_WRBACK, %eax
|
||||
xorl %edx, %edx
|
||||
wrmsr
|
||||
|
||||
/* Set SMRR mask. */
|
||||
movl $SMRRphysMask_MSR, %ecx
|
||||
movl $(~(CONFIG_SMM_TSEG_SIZE - 1) | MTRRphysMaskValid), %eax
|
||||
xorl %edx, %edx
|
||||
wrmsr
|
||||
|
||||
#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
|
||||
/*
|
||||
* IED base is top 4M of TSEG
|
||||
*/
|
||||
addl $(CONFIG_SMM_TSEG_SIZE - IED_SIZE), %ebx
|
||||
movl $(0x30000 + 0x8000 + 0x7eec), %eax
|
||||
addr32 movl %ebx, (%eax)
|
||||
#endif
|
||||
|
||||
skip_smrr:
|
||||
#endif
|
||||
|
||||
/* The next section of code is potentially southbridge specific */
|
||||
|
||||
|
|
|
|||
|
|
@ -280,6 +280,8 @@ void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_
|
|||
|
||||
void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts);
|
||||
int __attribute__((weak)) mainboard_apm_cnt(u8 data);
|
||||
#if !CONFIG_SMM_TSEG
|
||||
void smi_release_lock(void);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue