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cpu/intel/hyperthreading: Build only for selected models 

Implements intel_sibling_init() that is mostly superseded.

Change-Id: I4956493d8c0c6b922343e060d2d2bd0ec20f5bb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55201
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2021-05-29 21:54:26 +03:00
parent 34806cce60
commit 3ab6157ede
9 changed files with 4 additions and 7 deletions
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1
src/cpu/intel/model_f2x/Makefile.inc
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@ -1,4 +1,5 @@
subdirs-y += ../common subdirs-y += ../common
subdirs-y += ../hyperthreading
ramstage-y += model_f2x_init.c ramstage-y += model_f2x_init.c

3
src/cpu/intel/model_f3x/Makefile.inc
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@ -1,5 +1,8 @@
ramstage-y += model_f3x_init.c ramstage-y += model_f3x_init.c
subdirs-y += ../hyperthreading
subdirs-y += ../smm/gen1 subdirs-y += ../smm/gen1
ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-03-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-03-*)

1
src/cpu/intel/socket_441/Makefile.inc
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@ -4,7 +4,6 @@ subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache subdirs-y += ../../x86/cache
subdirs-y += ../microcode subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep subdirs-y += ../speedstep
bootblock-y += ../car/p4-netburst/cache_as_ram.S bootblock-y += ../car/p4-netburst/cache_as_ram.S

1
src/cpu/intel/socket_BGA956/Makefile.inc
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@ -4,7 +4,6 @@ subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache subdirs-y += ../../x86/cache
subdirs-y += ../microcode subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep subdirs-y += ../speedstep
bootblock-y += ../car/core2/cache_as_ram.S bootblock-y += ../car/core2/cache_as_ram.S

1
src/cpu/intel/socket_FCBGA559/Makefile.inc
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@ -4,7 +4,6 @@ subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache subdirs-y += ../../x86/cache
subdirs-y += ../microcode subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep subdirs-y += ../speedstep
bootblock-y += ../car/bootblock.c bootblock-y += ../car/bootblock.c

1
src/cpu/intel/socket_LGA775/Makefile.inc
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@ -9,7 +9,6 @@ subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache subdirs-y += ../../x86/cache
subdirs-y += ../microcode subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep subdirs-y += ../speedstep
bootblock-y += ../car/p4-netburst/cache_as_ram.S bootblock-y += ../car/p4-netburst/cache_as_ram.S

1
src/cpu/intel/socket_m/Makefile.inc
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@ -5,7 +5,6 @@ subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache subdirs-y += ../../x86/cache
subdirs-y += ../microcode subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep subdirs-y += ../speedstep
bootblock-y += ../car/core2/cache_as_ram.S bootblock-y += ../car/core2/cache_as_ram.S

1
src/cpu/intel/socket_mPGA604/Makefile.inc
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@ -4,7 +4,6 @@ subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache subdirs-y += ../../x86/cache
subdirs-y += ../microcode subdirs-y += ../microcode
subdirs-y += ../hyperthreading
bootblock-y += ../car/p4-netburst/cache_as_ram.S bootblock-y += ../car/p4-netburst/cache_as_ram.S
bootblock-y += ../car/bootblock.c bootblock-y += ../car/bootblock.c

1
src/cpu/intel/socket_p/Makefile.inc
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@ -5,7 +5,6 @@ subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache subdirs-y += ../../x86/cache
subdirs-y += ../microcode subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep subdirs-y += ../speedstep
bootblock-y += ../car/core2/cache_as_ram.S bootblock-y += ../car/core2/cache_as_ram.S