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drop USE_INIT should be USE_PRINTK_IN_CAR here. 

uint32_t should be u32
DEBUG_RAM_SETUP was failing on some northbridges
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5338 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-03-30 22:12:59 +00:00 committed by Stefan Reinauer
parent b01fe696d4
commit 3ac400e6e5
5 changed files with 38 additions and 30 deletions
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32
src/northbridge/intel/e7501/debug.c
View File

@ -39,7 +39,7 @@ static void dump_pci_device(unsigned dev)
for(i = 0; i < 256; i++) { for(i = 0; i < 256; i++) {
unsigned char val; unsigned char val;
if ((i & 0x0f) == 0) { if ((i & 0x0f) == 0) {
#if CONFIG_USE_INIT #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "\r\n%02x:",i); printk(BIOS_DEBUG, "\r\n%02x:",i);
#else #else
print_debug("\r\n"); print_debug("\r\n");
@ -48,7 +48,7 @@ static void dump_pci_device(unsigned dev)
#endif #endif
} }
val = pci_read_config8(dev, i); val = pci_read_config8(dev, i);
#if CONFIG_USE_INIT #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, " %02x", val); printk(BIOS_DEBUG, " %02x", val);
#else #else
print_debug_char(' '); print_debug_char(' ');
@ -101,7 +101,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
device = ctrl->channel0[i]; device = ctrl->channel0[i];
if (device) { if (device) {
int j; int j;
#if CONFIG_USE_INIT #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device); printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
#else #else
print_debug("dimm: "); print_debug("dimm: ");
@ -113,7 +113,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status; int status;
unsigned char byte; unsigned char byte;
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
#if CONFIG_USE_INIT #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "\r\n%02x: ", j); printk(BIOS_DEBUG, "\r\n%02x: ", j);
#else #else
print_debug("\r\n"); print_debug("\r\n");
@ -126,7 +126,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
break; break;
} }
byte = status & 0xff; byte = status & 0xff;
#if CONFIG_USE_INIT #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "%02x ", byte); printk(BIOS_DEBUG, "%02x ", byte);
#else #else
print_debug_hex8(byte); print_debug_hex8(byte);
@ -138,7 +138,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
device = ctrl->channel1[i]; device = ctrl->channel1[i];
if (device) { if (device) {
int j; int j;
#if CONFIG_USE_INIT #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
#else` #else`
print_debug("dimm: "); print_debug("dimm: ");
@ -150,7 +150,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status; int status;
unsigned char byte; unsigned char byte;
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
#if CONFIG_USE_INIT #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "\r\n%02x: ", j); printk(BIOS_DEBUG, "\r\n%02x: ", j);
#else #else
print_debug("\r\n"); print_debug("\r\n");
@ -163,7 +163,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
break; break;
} }
byte = status & 0xff; byte = status & 0xff;
#if CONFIG_USE_INIT #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "%02x ", byte); printk(BIOS_DEBUG, "%02x ", byte);
#else #else
print_debug_hex8(byte); print_debug_hex8(byte);
@ -181,7 +181,7 @@ static void dump_smbus_registers(void)
for(device = 1; device < 0x80; device++) { for(device = 1; device < 0x80; device++) {
int j; int j;
if( smbus_read_byte(device, 0) < 0 ) continue; if( smbus_read_byte(device, 0) < 0 ) continue;
#if CONFIG_USE_INIT #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "smbus: %02x", device); printk(BIOS_DEBUG, "smbus: %02x", device);
#else #else
print_debug("smbus: "); print_debug("smbus: ");
@ -195,7 +195,7 @@ static void dump_smbus_registers(void)
break; break;
} }
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
#if CONFIG_USE_INIT #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "\r\n%02x: ",j); printk(BIOS_DEBUG, "\r\n%02x: ",j);
#else #else
print_debug("\r\n"); print_debug("\r\n");
@ -204,7 +204,7 @@ static void dump_smbus_registers(void)
#endif #endif
} }
byte = status & 0xff; byte = status & 0xff;
#if CONFIG_USE_INIT #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "%02x ", byte); printk(BIOS_DEBUG, "%02x ", byte);
#else #else
print_debug_hex8(byte); print_debug_hex8(byte);
@ -219,7 +219,7 @@ static void dump_io_resources(unsigned port)
{ {
int i; int i;
#if CONFIG_USE_INIT #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "%04x:\r\n", port); printk(BIOS_DEBUG, "%04x:\r\n", port);
#else #else
print_debug_hex16(port); print_debug_hex16(port);
@ -228,7 +228,7 @@ static void dump_io_resources(unsigned port)
for(i=0;i<256;i++) { for(i=0;i<256;i++) {
uint8_t val; uint8_t val;
if ((i & 0x0f) == 0) { if ((i & 0x0f) == 0) {
#if CONFIG_USE_INIT #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "%02x:", i); printk(BIOS_DEBUG, "%02x:", i);
#else #else
print_debug_hex8(i); print_debug_hex8(i);
@ -236,7 +236,7 @@ static void dump_io_resources(unsigned port)
#endif #endif
} }
val = inb(port); val = inb(port);
#if CONFIG_USE_INIT #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, " %02x",val); printk(BIOS_DEBUG, " %02x",val);
#else #else
print_debug_char(' '); print_debug_char(' ');
@ -255,7 +255,7 @@ static void dump_mem(unsigned start, unsigned end)
print_debug("dump_mem:"); print_debug("dump_mem:");
for(i=start;i<end;i++) { for(i=start;i<end;i++) {
if((i & 0xf)==0) { if((i & 0xf)==0) {
#if CONFIG_USE_INIT #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "\r\n%08x:", i); printk(BIOS_DEBUG, "\r\n%08x:", i);
#else #else
print_debug("\r\n"); print_debug("\r\n");
@ -263,7 +263,7 @@ static void dump_mem(unsigned start, unsigned end)
print_debug(":"); print_debug(":");
#endif #endif
} }
#if CONFIG_USE_INIT #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
#else #else
print_debug(" "); print_debug(" ");

4
src/northbridge/intel/i440bx/raminit.c
View File

@ -36,7 +36,9 @@ Macros and definitions.
#define PRINT_DEBUG_HEX8(x) print_debug_hex8(x) #define PRINT_DEBUG_HEX8(x) print_debug_hex8(x)
#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x) #define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
#define PRINT_DEBUG_HEX32(x) print_debug_hex32(x) #define PRINT_DEBUG_HEX32(x) print_debug_hex32(x)
#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0)) // no dump_pci_device in src/northbridge/intel/i440bx
// #define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
#define DUMPNORTH()
#else #else
#define PRINT_DEBUG(x) #define PRINT_DEBUG(x)
#define PRINT_DEBUG_HEX8(x) #define PRINT_DEBUG_HEX8(x)

2
src/northbridge/intel/i82810/northbridge.c
View File

@ -208,8 +208,6 @@ static struct device_operations cpu_bus_ops = {
static void enable_dev(struct device *dev) static void enable_dev(struct device *dev)
{ {
struct device_path path;
/* Set the operations if it is a special bus type */ /* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
dev->ops = &pci_domain_ops; dev->ops = &pci_domain_ops;

16
src/northbridge/intel/i82810/raminit.c
View File

@ -30,12 +30,17 @@ Macros and definitions.
-----------------------------------------------------------------------------*/ -----------------------------------------------------------------------------*/
/* Debugging macros. */ /* Debugging macros. */
#define HAVE_ENOUGH_REGISTERS 0 /* Don't have enough registers to compile all
* debugging code with ROMCC
*/
#if CONFIG_DEBUG_RAM_SETUP #if CONFIG_DEBUG_RAM_SETUP
#define PRINT_DEBUG(x) print_debug(x) #define PRINT_DEBUG(x) print_debug(x)
#define PRINT_DEBUG_HEX8(x) print_debug_hex8(x) #define PRINT_DEBUG_HEX8(x) print_debug_hex8(x)
#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x) #define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
#define PRINT_DEBUG_HEX32(x) print_debug_hex32(x) #define PRINT_DEBUG_HEX32(x) print_debug_hex32(x)
#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0)) // no dump_pci_device in src/northbridge/intel/i82810/
// #define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
#define DUMPNORTH()
#else #else
#define PRINT_DEBUG(x) #define PRINT_DEBUG(x)
#define PRINT_DEBUG_HEX8(x) #define PRINT_DEBUG_HEX8(x)
@ -138,26 +143,29 @@ static void do_ram_command(u8 command)
drp = (drp >> (i * 4)) & 0x0f; drp = (drp >> (i * 4)) & 0x0f;
dimm_size = translate_i82810_to_mb[drp]; dimm_size = translate_i82810_to_mb[drp];
addr = (dimm_start * 1024 * 1024) + addr_offset;
if (dimm_size) { if (dimm_size) {
addr = (dimm_start * 1024 * 1024) + addr_offset;
#if HAVE_ENOUGH_REGISTERS
PRINT_DEBUG(" Sending RAM command 0x"); PRINT_DEBUG(" Sending RAM command 0x");
PRINT_DEBUG_HEX8(reg8); PRINT_DEBUG_HEX8(reg8);
PRINT_DEBUG(" to 0x"); PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(addr); PRINT_DEBUG_HEX32(addr);
PRINT_DEBUG("\r\n"); PRINT_DEBUG("\r\n");
#endif
read32(addr); read32(addr);
} }
dimm_bank = translate_i82810_to_bank[drp]; dimm_bank = translate_i82810_to_bank[drp];
addr = ((dimm_start + dimm_bank) * 1024 * 1024) + addr_offset;
if (dimm_bank) { if (dimm_bank) {
addr = ((dimm_start + dimm_bank) * 1024 * 1024) + addr_offset;
#if HAVE_ENOUGH_REGISTERS
PRINT_DEBUG(" Sending RAM command 0x"); PRINT_DEBUG(" Sending RAM command 0x");
PRINT_DEBUG_HEX8(reg8); PRINT_DEBUG_HEX8(reg8);
PRINT_DEBUG(" to 0x"); PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(addr); PRINT_DEBUG_HEX32(addr);
PRINT_DEBUG("\r\n"); PRINT_DEBUG("\r\n");
#endif
read32(addr); read32(addr);
} }

12
src/northbridge/intel/i82830/raminit.c
View File

@ -67,9 +67,9 @@ Macros and definitions.
DIMM-initialization functions. DIMM-initialization functions.
-----------------------------------------------------------------------------*/ -----------------------------------------------------------------------------*/
static void do_ram_command(uint32_t command) static void do_ram_command(u32 command)
{ {
uint32_t reg32; u32 reg32;
/* Configure the RAM command. */ /* Configure the RAM command. */
reg32 = pci_read_config32(NORTHBRIDGE, DRC); reg32 = pci_read_config32(NORTHBRIDGE, DRC);
@ -82,7 +82,7 @@ static void do_ram_command(uint32_t command)
PRINT_DEBUG("\r\n"); PRINT_DEBUG("\r\n");
} }
static void ram_read32(uint8_t dimm_start, uint32_t offset) static void ram_read32(u8 dimm_start, u32 offset)
{ {
if (offset == 0x55aa55aa) { if (offset == 0x55aa55aa) {
PRINT_DEBUG(" Reading RAM at 0x"); PRINT_DEBUG(" Reading RAM at 0x");
@ -114,7 +114,7 @@ static void ram_read32(uint8_t dimm_start, uint32_t offset)
static void initialize_dimm_rows(void) static void initialize_dimm_rows(void)
{ {
int i, row; int i, row;
uint8_t dimm_start, dimm_end; u8 dimm_start, dimm_end;
unsigned device; unsigned device;
dimm_start = 0; dimm_start = 0;
@ -487,7 +487,7 @@ static void sdram_set_registers(void)
static void northbridge_set_registers(void) static void northbridge_set_registers(void)
{ {
uint16_t value; u16 value;
int igd_memory = 0; int igd_memory = 0;
PRINT_DEBUG("Setting initial nothbridge registers....\r\n"); PRINT_DEBUG("Setting initial nothbridge registers....\r\n");
@ -542,7 +542,7 @@ static void northbridge_set_registers(void)
static void sdram_initialize(void) static void sdram_initialize(void)
{ {
int i; int i;
uint32_t reg32; u32 reg32;
/* Setup Initial SDRAM Registers */ /* Setup Initial SDRAM Registers */
sdram_set_registers(); sdram_set_registers();