diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 8c8b1b7bca..3df4bd763f 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -84,7 +84,7 @@ config DCACHE_RAM_BASE
 
 config DCACHE_RAM_SIZE
 	hex "Length in bytes of cache-as-RAM"
-	default 0x10000
+	default 0x40000
 	help
 	  The size of the cache-as-ram region required during bootblock
 	  and/or romstage.
@@ -199,10 +199,6 @@ config NHLT_SSM4567
 	help
 	  Include DSP firmware settings for ssm4567 smart amplifier.
 
-config DCACHE_RAM_SIZE_TOTAL
-	hex
-	default 0x40000
-
 config SKIP_FSP_CAR
 	bool "Skip cache as RAM setup in FSP"
 	default y
diff --git a/src/soc/intel/skylake/bootblock/cache_as_ram.S b/src/soc/intel/skylake/bootblock/cache_as_ram.S
index 89a3cf091a..3f8f0f0fb9 100644
--- a/src/soc/intel/skylake/bootblock/cache_as_ram.S
+++ b/src/soc/intel/skylake/bootblock/cache_as_ram.S
@@ -116,7 +116,7 @@ clear_var_mtrr:
 
 	/* Configure the MTRR mask for the size region */
 	mov	$MTRR_PHYS_MASK(0), %ecx
-	mov	$CONFIG_DCACHE_RAM_SIZE_TOTAL, %eax	/* size mask */
+	mov	$CONFIG_DCACHE_RAM_SIZE, %eax	/* size mask */
 	dec	%eax
 	not	%eax
 	or	$MTRR_PHYS_MASK_VALID, %eax
@@ -216,7 +216,7 @@ find_llc_subleaf:
 	wrmsr
 
 	movl	$CONFIG_DCACHE_RAM_BASE, %edi
-	movl	$CONFIG_DCACHE_RAM_SIZE_TOTAL, %ecx
+	movl	$CONFIG_DCACHE_RAM_SIZE, %ecx
 	shr	$0x02, %ecx
 	movl	$CACHE_INIT_VALUE, %eax
 	cld
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index fda60875f2..0ec2f99e63 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -93,7 +93,7 @@ void soc_memory_init_params(struct romstage_params *params,
 	upd->DdrFreqLimit = config->DdrFreqLimit;
 	if (IS_ENABLED(CONFIG_SKIP_FSP_CAR)) {
 		upd->FspCarBase = CONFIG_DCACHE_RAM_BASE;
-		upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE_TOTAL;
+		upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE;
 	}
 }