nb/amd/agesa/*/northbridge.c: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: If7cac72e0bbdefdb4b6e2697df69a061a23e8684 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes Haouas
Martin L Roth
parent
f58c787db5
commit
3adfde9c6a
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@ -44,7 +44,7 @@ static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg,
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/* io range allocation */
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tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) |
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((io_max & 0xf0) << (12 - 4)); //limit
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pci_write_config32(__f1_dev[0], reg+4, tempreg);
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pci_write_config32(__f1_dev[0], reg + 4, tempreg);
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tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); //base :ISA and VGA ?
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pci_write_config32(__f1_dev[0], reg, tempreg);
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@ -553,7 +553,7 @@ static void domain_set_resources(struct device *dev)
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/* See if we need a hole from 0xa0000 (640K) to 0xbffff (768K) */
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if (basek < 640 && sizek > 768) {
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printk(BIOS_DEBUG,"adsr - 0xa0000 to 0xbffff resource.\n");
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printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n");
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ram_resource_kb(dev, (idx | 0), basek, 640 - basek);
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idx += 0x10;
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basek = 768;
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@ -718,10 +718,10 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
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/* SRAT */
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current = ALIGN(current, 8);
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printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
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srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
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srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT);
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if (srat != NULL) {
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memcpy((void *)current, srat, srat->header.length);
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srat = (acpi_srat_t *) current;
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srat = (acpi_srat_t *)current;
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current += srat->header.length;
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acpi_add_table(rsdp, srat);
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}
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@ -732,10 +732,10 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
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/* SLIT */
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current = ALIGN(current, 8);
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printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
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slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
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slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT);
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if (slit != NULL) {
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memcpy((void *)current, slit, slit->header.length);
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slit = (acpi_slit_t *) current;
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slit = (acpi_slit_t *)current;
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current += slit->header.length;
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acpi_add_table(rsdp, slit);
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}
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@ -746,10 +746,10 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
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/* SSDT */
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current = ALIGN(current, 16);
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printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current);
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alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
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alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB);
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if (alib != NULL) {
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memcpy((void *)current, alib, alib->length);
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alib = (acpi_header_t *) current;
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alib = (acpi_header_t *)current;
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current += alib->length;
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acpi_add_table(rsdp, (void *)alib);
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} else {
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@ -760,15 +760,15 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
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/* Keep the comment for a while. */
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current = ALIGN(current, 16);
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printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current);
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ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
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ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE);
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if (ssdt != NULL) {
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hexdump(ssdt, ssdt->length);
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patch_ssdt_processor_scope(ssdt);
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hexdump(ssdt, ssdt->length);
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memcpy((void *)current, ssdt, ssdt->length);
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ssdt = (acpi_header_t *) current;
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ssdt = (acpi_header_t *)current;
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current += ssdt->length;
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acpi_add_table(rsdp,ssdt);
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acpi_add_table(rsdp, ssdt);
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} else {
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printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n");
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}
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@ -783,7 +783,7 @@ static struct device_operations northbridge_operations = {
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.acpi_fill_ssdt = northbridge_fill_ssdt_generator,
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.write_acpi_tables = agesa_write_acpi_tables,
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.init = northbridge_init,
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.enable = 0,.ops_pci = 0,
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.enable = 0, .ops_pci = 0,
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};
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static const struct pci_driver northbridge_driver __pci_driver = {
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@ -38,10 +38,10 @@ static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg,
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u32 i;
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u32 tempreg;
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/* io range allocation */
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tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit
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tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | ((io_max & 0xf0) << (12 - 4)); //limit
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for (i = 0; i < node_nums; i++)
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pci_write_config32(__f1_dev[i], reg+4, tempreg);
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tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
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pci_write_config32(__f1_dev[i], reg + 4, tempreg);
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tempreg = 3 /*| (3 << 4)*/ | ((io_min & 0xf0) << (12 - 4)); //base :ISA and VGA ?
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for (i = 0; i < node_nums; i++)
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pci_write_config32(__f1_dev[i], reg, tempreg);
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}
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@ -51,10 +51,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
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u32 i;
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u32 tempreg;
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/* io range allocation */
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tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit
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tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); //limit
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for (i = 0; i < nodes; i++)
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pci_write_config32(__f1_dev[i], reg+4, tempreg);
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tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
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pci_write_config32(__f1_dev[i], reg + 4, tempreg);
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tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00);
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for (i = 0; i < node_nums; i++)
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pci_write_config32(__f1_dev[i], reg, tempreg);
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}
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@ -73,7 +73,7 @@ static void get_fx_devs(void)
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__f2_dev[i] = get_node_pci(i, 2);
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__f4_dev[i] = get_node_pci(i, 4);
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if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
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fx_devs = i+1;
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fx_devs = i + 1;
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}
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if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
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die("Cannot find 0:0x18.[0|1]\n");
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@ -338,10 +338,10 @@ static void set_resource(struct device *dev, struct resource *resource, u32 node
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link_num = IOINDEX_LINK(resource->index);
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if (resource->flags & IORESOURCE_IO) {
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set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
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set_io_addr_reg(dev, nodeid, link_num, reg, rbase >> 8, rend >> 8);
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}
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else if (resource->flags & IORESOURCE_MEM) {
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set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums);// [39:8]
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set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >> 24), rbase >> 8, rend >> 8, node_nums);// [39:8]
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}
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resource->flags |= IORESOURCE_STORED;
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snprintf(buf, sizeof(buf), " <node %x link %x>",
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@ -365,7 +365,7 @@ static void create_vga_resource(struct device *dev, unsigned int nodeid)
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#if CONFIG(MULTIPLE_VGA_ADAPTERS)
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extern struct device *vga_pri; // the primary vga device, defined in device.c
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printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
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link->secondary,link->subordinate);
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link->secondary, link->subordinate);
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/* We need to make sure the vga_pri is under the link */
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if ((vga_pri->bus->secondary >= link->secondary) &&
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(vga_pri->bus->secondary <= link->subordinate))
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@ -484,7 +484,7 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
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ivrs = agesawrapper_getlateinitptr(PICK_IVRS);
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if (ivrs != NULL) {
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memcpy((void *)current, ivrs, ivrs->length);
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ivrs = (acpi_header_t *) current;
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ivrs = (acpi_header_t *)current;
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current += ivrs->length;
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acpi_add_table(rsdp, ivrs);
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} else {
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@ -494,10 +494,10 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
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/* SRAT */
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current = ALIGN(current, 8);
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printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
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srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
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srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT);
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if (srat != NULL) {
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memcpy((void *)current, srat, srat->header.length);
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srat = (acpi_srat_t *) current;
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srat = (acpi_srat_t *)current;
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current += srat->header.length;
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acpi_add_table(rsdp, srat);
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} else {
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@ -507,10 +507,10 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
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/* SLIT */
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current = ALIGN(current, 8);
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printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
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slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
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slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT);
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if (slit != NULL) {
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memcpy((void *)current, slit, slit->header.length);
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slit = (acpi_slit_t *) current;
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slit = (acpi_slit_t *)current;
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current += slit->header.length;
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acpi_add_table(rsdp, slit);
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} else {
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@ -520,10 +520,10 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
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/* ALIB */
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current = ALIGN(current, 16);
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printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current);
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alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
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alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB);
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if (alib != NULL) {
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memcpy((void *)current, alib, alib->length);
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alib = (acpi_header_t *) current;
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alib = (acpi_header_t *)current;
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current += alib->length;
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acpi_add_table(rsdp, (void *)alib);
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}
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@ -535,17 +535,17 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
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/* SSDT */
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current = ALIGN(current, 16);
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printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
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ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
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ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE);
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if (ssdt != NULL) {
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patch_ssdt_processor_scope(ssdt);
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memcpy((void *)current, ssdt, ssdt->length);
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ssdt = (acpi_header_t *) current;
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ssdt = (acpi_header_t *)current;
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current += ssdt->length;
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}
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else {
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printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n");
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}
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acpi_add_table(rsdp,ssdt);
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acpi_add_table(rsdp, ssdt);
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printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
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@ -583,7 +583,7 @@ static void domain_read_resources(struct device *dev)
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/* Find the already assigned resource pairs */
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get_fx_devs();
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for (reg = 0x80; reg <= 0xd8; reg+= 0x08) {
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for (reg = 0x80; reg <= 0xd8; reg += 0x08) {
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u32 base, limit;
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base = f1_read_config32(reg);
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limit = f1_read_config32(reg + 0x04);
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@ -592,9 +592,9 @@ static void domain_read_resources(struct device *dev)
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unsigned int nodeid, reg_link;
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struct device *reg_dev;
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if (reg < 0xc0) { // mmio
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nodeid = (limit & 0xf) + (base&0x30);
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nodeid = (limit & 0xf) + (base & 0x30);
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} else { // io
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nodeid = (limit & 0xf) + ((base>>4)&0x30);
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nodeid = (limit & 0xf) + ((base >> 4) & 0x30);
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}
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reg_link = (limit >> 4) & 7;
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reg_dev = __f0_dev[nodeid];
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@ -647,7 +647,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
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resource_t base_k, limit_k;
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if (!get_dram_base_limit(i, &base_k, &limit_k))
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continue; // no memory on this node
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if (base_k > 4 *1024 * 1024) break; // don't need to go to check
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if (base_k > 4 * 1024 * 1024) break; // don't need to go to check
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if (limitk_pri != base_k) { // we find the hole
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mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G
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mem_hole.node_id = i;
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@ -679,12 +679,12 @@ static void domain_set_resources(struct device *dev)
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// amdk8, too.
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mmio_basek = pci_tolm >> 10;
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/* Round mmio_basek to something the processor can support */
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mmio_basek &= ~((1 << 6) -1);
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mmio_basek &= ~((1 << 6) - 1);
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// FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
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// MMIO hole. If you fix this here, please fix amdk8, too.
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/* Round the mmio hole to 64M */
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mmio_basek &= ~((64*1024) - 1);
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mmio_basek &= ~((64 * 1024) - 1);
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#if CONFIG_HW_MEM_HOLE_SIZEK != 0
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/* if the hw mem hole is already set in raminit stage, here we will compare
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@ -719,7 +719,7 @@ static void domain_set_resources(struct device *dev)
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}
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/* split the region to accommodate pci memory space */
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if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
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if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) {
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if (basek <= mmio_basek) {
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unsigned int pre_sizek;
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pre_sizek = mmio_basek - basek;
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@ -730,13 +730,13 @@ static void domain_set_resources(struct device *dev)
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}
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basek = mmio_basek;
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}
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if ((basek + sizek) <= 4*1024*1024) {
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if ((basek + sizek) <= 4 * 1024 * 1024) {
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sizek = 0;
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}
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else {
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uint64_t topmem2 = amd_topmem2();
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basek = 4*1024*1024;
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sizek = topmem2/1024 - basek;
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basek = 4 * 1024 * 1024;
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sizek = topmem2 / 1024 - basek;
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}
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}
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@ -763,15 +763,15 @@ static struct device_operations pci_domain_ops = {
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static void sysconf_init(struct device *dev) // first node
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{
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sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1
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node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
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sblink = (pci_read_config32(dev, 0x64) >> 8) & 7; // don't forget sublink1
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node_nums = ((pci_read_config32(dev, 0x60) >> 4) & 7) + 1; //NodeCnt[2:0]
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}
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static void cpu_bus_scan(struct device *dev)
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{
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struct bus *cpu_bus;
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struct device *dev_mc;
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int i,j;
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int i, j;
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int coreid_bits;
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int core_max = 0;
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unsigned int ApicIdCoreIdSize;
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@ -790,7 +790,7 @@ static void cpu_bus_scan(struct device *dev)
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coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
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core_max = 1 << (coreid_bits & 0x000F); //mnc
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ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);
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ApicIdCoreIdSize = ((cpuid_ecx(0x80000008) >> 12) & 0xF);
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if (ApicIdCoreIdSize) {
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core_nums = (1 << ApicIdCoreIdSize) - 1;
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} else {
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@ -872,7 +872,7 @@ static void cpu_bus_scan(struct device *dev)
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lapicid_start = (lapicid_start + 1) * core_max;
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printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
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}
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u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
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u32 apic_id = (lapicid_start * (i / modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
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printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
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i, j, apic_id);
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@ -38,10 +38,10 @@ static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg,
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u32 i;
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u32 tempreg;
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/* io range allocation */
|
||||
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit
|
||||
tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | ((io_max & 0xf0) << (12 - 4)); //limit
|
||||
for (i = 0; i < node_nums; i++)
|
||||
pci_write_config32(__f1_dev[i], reg+4, tempreg);
|
||||
tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
|
||||
pci_write_config32(__f1_dev[i], reg + 4, tempreg);
|
||||
tempreg = 3 /*| (3 << 4)*/ | ((io_min & 0xf0) << (12 - 4)); //base :ISA and VGA ?
|
||||
for (i = 0; i < node_nums; i++)
|
||||
pci_write_config32(__f1_dev[i], reg, tempreg);
|
||||
}
|
||||
|
|
@ -51,10 +51,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
|
|||
u32 i;
|
||||
u32 tempreg;
|
||||
/* io range allocation */
|
||||
tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit
|
||||
tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); //limit
|
||||
for (i = 0; i < nodes; i++)
|
||||
pci_write_config32(__f1_dev[i], reg+4, tempreg);
|
||||
tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
|
||||
pci_write_config32(__f1_dev[i], reg + 4, tempreg);
|
||||
tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00);
|
||||
for (i = 0; i < node_nums; i++)
|
||||
pci_write_config32(__f1_dev[i], reg, tempreg);
|
||||
}
|
||||
|
|
@ -73,7 +73,7 @@ static void get_fx_devs(void)
|
|||
__f2_dev[i] = get_node_pci(i, 2);
|
||||
__f4_dev[i] = get_node_pci(i, 4);
|
||||
if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
|
||||
fx_devs = i+1;
|
||||
fx_devs = i + 1;
|
||||
}
|
||||
if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
|
||||
die("Cannot find 0:0x18.[0|1]\n");
|
||||
|
|
@ -332,10 +332,10 @@ static void set_resource(struct device *dev, struct resource *resource, u32 node
|
|||
link_num = IOINDEX_LINK(resource->index);
|
||||
|
||||
if (resource->flags & IORESOURCE_IO) {
|
||||
set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
|
||||
set_io_addr_reg(dev, nodeid, link_num, reg, rbase >> 8, rend >> 8);
|
||||
}
|
||||
else if (resource->flags & IORESOURCE_MEM) {
|
||||
set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums);// [39:8]
|
||||
set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >> 24), rbase >> 8, rend >> 8, node_nums);// [39:8]
|
||||
}
|
||||
resource->flags |= IORESOURCE_STORED;
|
||||
snprintf(buf, sizeof(buf), " <node %x link %x>",
|
||||
|
|
@ -359,7 +359,7 @@ static void create_vga_resource(struct device *dev, unsigned int nodeid)
|
|||
#if CONFIG(MULTIPLE_VGA_ADAPTERS)
|
||||
extern struct device *vga_pri; // the primary vga device, defined in device.c
|
||||
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
|
||||
link->secondary,link->subordinate);
|
||||
link->secondary, link->subordinate);
|
||||
/* We need to make sure the vga_pri is under the link */
|
||||
if ((vga_pri->bus->secondary >= link->secondary) &&
|
||||
(vga_pri->bus->secondary <= link->subordinate))
|
||||
|
|
@ -478,7 +478,7 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
|
|||
ivrs = agesawrapper_getlateinitptr(PICK_IVRS);
|
||||
if (ivrs != NULL) {
|
||||
memcpy((void *)current, ivrs, ivrs->length);
|
||||
ivrs = (acpi_header_t *) current;
|
||||
ivrs = (acpi_header_t *)current;
|
||||
current += ivrs->length;
|
||||
acpi_add_table(rsdp, ivrs);
|
||||
} else {
|
||||
|
|
@ -488,10 +488,10 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
|
|||
/* SRAT */
|
||||
current = ALIGN(current, 8);
|
||||
printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
|
||||
srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
|
||||
srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT);
|
||||
if (srat != NULL) {
|
||||
memcpy((void *)current, srat, srat->header.length);
|
||||
srat = (acpi_srat_t *) current;
|
||||
srat = (acpi_srat_t *)current;
|
||||
current += srat->header.length;
|
||||
acpi_add_table(rsdp, srat);
|
||||
} else {
|
||||
|
|
@ -501,10 +501,10 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
|
|||
/* SLIT */
|
||||
current = ALIGN(current, 8);
|
||||
printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
|
||||
slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
|
||||
slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT);
|
||||
if (slit != NULL) {
|
||||
memcpy((void *)current, slit, slit->header.length);
|
||||
slit = (acpi_slit_t *) current;
|
||||
slit = (acpi_slit_t *)current;
|
||||
current += slit->header.length;
|
||||
acpi_add_table(rsdp, slit);
|
||||
} else {
|
||||
|
|
@ -514,10 +514,10 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
|
|||
/* ALIB */
|
||||
current = ALIGN(current, 16);
|
||||
printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current);
|
||||
alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
|
||||
alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB);
|
||||
if (alib != NULL) {
|
||||
memcpy((void *)current, alib, alib->length);
|
||||
alib = (acpi_header_t *) current;
|
||||
alib = (acpi_header_t *)current;
|
||||
current += alib->length;
|
||||
acpi_add_table(rsdp, (void *)alib);
|
||||
}
|
||||
|
|
@ -529,17 +529,17 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
|
|||
/* SSDT */
|
||||
current = ALIGN(current, 16);
|
||||
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
|
||||
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
|
||||
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE);
|
||||
if (ssdt != NULL) {
|
||||
patch_ssdt_processor_scope(ssdt);
|
||||
memcpy((void *)current, ssdt, ssdt->length);
|
||||
ssdt = (acpi_header_t *) current;
|
||||
ssdt = (acpi_header_t *)current;
|
||||
current += ssdt->length;
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n");
|
||||
}
|
||||
acpi_add_table(rsdp,ssdt);
|
||||
acpi_add_table(rsdp, ssdt);
|
||||
|
||||
printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
|
||||
|
||||
|
|
@ -595,7 +595,7 @@ static void domain_read_resources(struct device *dev)
|
|||
|
||||
/* Find the already assigned resource pairs */
|
||||
get_fx_devs();
|
||||
for (reg = 0x80; reg <= 0xd8; reg+= 0x08) {
|
||||
for (reg = 0x80; reg <= 0xd8; reg += 0x08) {
|
||||
u32 base, limit;
|
||||
base = f1_read_config32(reg);
|
||||
limit = f1_read_config32(reg + 0x04);
|
||||
|
|
@ -604,9 +604,9 @@ static void domain_read_resources(struct device *dev)
|
|||
unsigned int nodeid, reg_link;
|
||||
struct device *reg_dev;
|
||||
if (reg < 0xc0) { // mmio
|
||||
nodeid = (limit & 0xf) + (base&0x30);
|
||||
nodeid = (limit & 0xf) + (base & 0x30);
|
||||
} else { // io
|
||||
nodeid = (limit & 0xf) + ((base>>4)&0x30);
|
||||
nodeid = (limit & 0xf) + ((base >> 4) & 0x30);
|
||||
}
|
||||
reg_link = (limit >> 4) & 7;
|
||||
reg_dev = __f0_dev[nodeid];
|
||||
|
|
@ -659,7 +659,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
|
|||
resource_t base_k, limit_k;
|
||||
if (!get_dram_base_limit(i, &base_k, &limit_k))
|
||||
continue; // no memory on this node
|
||||
if (base_k > 4 *1024 * 1024) break; // don't need to go to check
|
||||
if (base_k > 4 * 1024 * 1024) break; // don't need to go to check
|
||||
if (limitk_pri != base_k) { // we find the hole
|
||||
mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G
|
||||
mem_hole.node_id = i;
|
||||
|
|
@ -691,12 +691,12 @@ static void domain_set_resources(struct device *dev)
|
|||
// amdk8, too.
|
||||
mmio_basek = pci_tolm >> 10;
|
||||
/* Round mmio_basek to something the processor can support */
|
||||
mmio_basek &= ~((1 << 6) -1);
|
||||
mmio_basek &= ~((1 << 6) - 1);
|
||||
|
||||
// FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
|
||||
// MMIO hole. If you fix this here, please fix amdk8, too.
|
||||
/* Round the mmio hole to 64M */
|
||||
mmio_basek &= ~((64*1024) - 1);
|
||||
mmio_basek &= ~((64 * 1024) - 1);
|
||||
|
||||
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
|
||||
/* if the hw mem hole is already set in raminit stage, here we will compare
|
||||
|
|
@ -732,7 +732,7 @@ static void domain_set_resources(struct device *dev)
|
|||
//printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk);
|
||||
|
||||
/* split the region to accommodate pci memory space */
|
||||
if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
|
||||
if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) {
|
||||
if (basek <= mmio_basek) {
|
||||
unsigned int pre_sizek;
|
||||
pre_sizek = mmio_basek - basek;
|
||||
|
|
@ -743,13 +743,13 @@ static void domain_set_resources(struct device *dev)
|
|||
}
|
||||
basek = mmio_basek;
|
||||
}
|
||||
if ((basek + sizek) <= 4*1024*1024) {
|
||||
if ((basek + sizek) <= 4 * 1024 * 1024) {
|
||||
sizek = 0;
|
||||
}
|
||||
else {
|
||||
uint64_t topmem2 = amd_topmem2();
|
||||
basek = 4*1024*1024;
|
||||
sizek = topmem2/1024 - basek;
|
||||
basek = 4 * 1024 * 1024;
|
||||
sizek = topmem2 / 1024 - basek;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -785,15 +785,15 @@ static struct device_operations pci_domain_ops = {
|
|||
|
||||
static void sysconf_init(struct device *dev) // first node
|
||||
{
|
||||
sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1
|
||||
node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
|
||||
sblink = (pci_read_config32(dev, 0x64) >> 8) & 7; // don't forget sublink1
|
||||
node_nums = ((pci_read_config32(dev, 0x60) >> 4) & 7) + 1; //NodeCnt[2:0]
|
||||
}
|
||||
|
||||
static void cpu_bus_scan(struct device *dev)
|
||||
{
|
||||
struct bus *cpu_bus;
|
||||
struct device *dev_mc;
|
||||
int i,j;
|
||||
int i, j;
|
||||
int coreid_bits;
|
||||
int core_max = 0;
|
||||
unsigned int ApicIdCoreIdSize;
|
||||
|
|
@ -812,7 +812,7 @@ static void cpu_bus_scan(struct device *dev)
|
|||
coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
|
||||
core_max = 1 << (coreid_bits & 0x000F); //mnc
|
||||
|
||||
ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);
|
||||
ApicIdCoreIdSize = ((cpuid_ecx(0x80000008) >> 12) & 0xF);
|
||||
if (ApicIdCoreIdSize) {
|
||||
core_nums = (1 << ApicIdCoreIdSize) - 1;
|
||||
} else {
|
||||
|
|
@ -894,7 +894,7 @@ static void cpu_bus_scan(struct device *dev)
|
|||
lapicid_start = (lapicid_start + 1) * core_max;
|
||||
printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
|
||||
}
|
||||
u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
|
||||
u32 apic_id = (lapicid_start * (i / modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
|
||||
printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
|
||||
i, j, apic_id);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue