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mb/starlabs/lite/glk: Organise USB ports by hardware port 

Group the USB ports by hardware ports, rather than separate USB 2.0 and
3.0 interfaces.

This change also corrects the daughterboard USB 3.0 port number.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib6a934a1e5e65fe387c63b78cbe80e45e97e0a8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64796
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2022-05-30 10:59:20 +01:00 committed by Felix Held
parent b02c90d146
commit 3ae95b2630
1 changed files with 7 additions and 9 deletions
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16
src/mainboard/starlabs/lite/variants/glk/devicetree.cb
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@ -86,25 +86,23 @@ chip soc/intel/apollolake
device pci 14.0 off end # PCIe-B 0 Slot2
device pci 14.1 off end # PCIe-B 1 Onboard M2 Slot(Wifi/BT)
device pci 15.0 on # XHCI
### USB 2.0 Devices
# Motherboard USB Type C
register "usb2_port[0]" = "PORT_EN(OC_SKIP)"
register "usb3_port[1]" = "PORT_EN(OC_SKIP)"
# Bluetooth
register "usb2_port[2]" = "PORT_EN(OC_SKIP)"
# Motherboard USB 3.0
register "usb2_port[3]" = "PORT_EN(OC1)"
register "usb3_port[0]" = "PORT_EN(OC1)"
# Daughterboard USB 3.0
register "usb2_port[5]" = "PORT_EN(OC_SKIP)"
register "usb3_port[4]" = "PORT_EN(OC_SKIP)"
# Daughterboard SD Card
register "usb2_port[6]" = "PORT_EN(OC_SKIP)"
### USB 3.0 Devices
# Motherboard USB 3.0
register "usb3_port[0]" = "PORT_EN(OC1)"
# Motherboard USB Type C
register "usb3_port[1]" = "PORT_EN(OC_SKIP)"
# Daughterboard USB 3.0
register "usb3_port[2]" = "PORT_EN(OC_SKIP)"
end
device pci 15.1 off end # XDCI
device pci 16.0 off end # I2C0