IEI Kino Fam10 ACPI table fixes.
Fix the ACPI IRQ routing. Also, fix the SSDT generations and TOM2 fixup. Change-Id: Ica4a992d11bab63a510238dcd468b9fe80136def Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/628 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Dave Frodin
Marc Jones
parent
a22f78b828
commit
3aea95803d
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@ -31,6 +31,8 @@ Scope(\_SB) {
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/* NB devices */
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/* Bus 0, Dev 0 - RS780 Host Controller */
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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Package(){0x0001FFFF, 0, INTC, 0 },
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Package(){0x0001FFFF, 1, INTD, 0 },
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, INTC, 0 },
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Package(){0x0002FFFF, 1, INTD, 0 },
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@ -57,22 +59,45 @@ Scope(\_SB) {
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Package(){0x0007FFFF, 1, INTA, 0 },
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Package(){0x0007FFFF, 2, INTB, 0 },
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Package(){0x0007FFFF, 3, INTC, 0 },
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Package(){0x0009FFFF, 0, INTB, 0 },
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Package(){0x0009FFFF, 1, INTC, 0 },
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Package(){0x0009FFFF, 2, INTD, 0 },
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Package(){0x0009FFFF, 3, INTA, 0 },
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Package(){0x000AFFFF, 0, INTC, 0 },
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Package(){0x000AFFFF, 1, INTD, 0 },
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Package(){0x000AFFFF, 2, INTA, 0 },
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Package(){0x000AFFFF, 3, INTB, 0 },
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Package(){0x000BFFFF, 0, INTD, 0 },
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Package(){0x000BFFFF, 1, INTA, 0 },
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Package(){0x000BFFFF, 2, INTB, 0 },
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Package(){0x000BFFFF, 3, INTC, 0 },
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Package(){0x000CFFFF, 0, INTA, 0 },
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Package(){0x000CFFFF, 1, INTB, 0 },
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Package(){0x000CFFFF, 2, INTC, 0 },
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Package(){0x000CFFFF, 3, INTD, 0 },
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/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
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/* SB devices */
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/* Bus 0, Dev 17 - SATA controller #2 */
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/* Bus 0, Dev 18 - SATA controller #1 */
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Package(){0x0011FFFF, 0, INTA, 0 },
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Package(){0x0011FFFF, 0, INTG, 0 },
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/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
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* EHCI, dev 18, 19 func 2 */
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Package(){0x0012FFFF, 0, INTA, 0 },
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Package(){0x0012FFFF, 1, INTB, 0 },
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Package(){0x0012FFFF, 2, INTC, 0 },
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Package(){0x0012FFFF, 3, INTD, 0 },
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Package(){0x0013FFFF, 0, INTC, 0 },
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Package(){0x0013FFFF, 1, INTD, 0 },
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Package(){0x0013FFFF, 2, INTA, 0 },
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Package(){0x0013FFFF, 3, INTB, 0 },
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/* Package(){0x0014FFFF, 1, INTA, 0 }, */
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@ -81,6 +106,12 @@ Scope(\_SB) {
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Package(){0x0014FFFF, 1, INTB, 0 },
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Package(){0x0014FFFF, 2, INTC, 0 },
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Package(){0x0014FFFF, 3, INTD, 0 },
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/* Package(){0x0015FFFF, 0, INTA, 0 },
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Package(){0x0015FFFF, 1, INTB, 0 },
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Package(){0x0015FFFF, 2, INTC, 0 },
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Package(){0x0015FFFF, 3, INTD, 0 },
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*/
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})
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Name(APR0, Package(){
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@ -129,11 +160,13 @@ Scope(\_SB) {
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/* Package(){0x0009FFFF, 1, 0, 16 }, */
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/* Package(){0x0009FFFF, 2, 0, 17 }, */
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/* Package(){0x0009FFFF, 3, 0, 18 }, */
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/* Bus 0, Dev A - PCIe Bridge for network card */
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Package(){0x000AFFFF, 0, 0, 18 },
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/* Package(){0x000AFFFF, 1, 0, 16 }, */
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/* Package(){0x000AFFFF, 2, 0, 17 }, */
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/* Package(){0x000AFFFF, 3, 0, 18 }, */
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/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
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/* SB devices in APIC mode */
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@ -146,41 +179,34 @@ Scope(\_SB) {
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Package(){0x0012FFFF, 0, 0, 16 },
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Package(){0x0012FFFF, 1, 0, 17 },
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Package(){0x0012FFFF, 2, 0, 18 },
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Package(){0x0012FFFF, 3, 0, 19 },
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Package(){0x0013FFFF, 0, 0, 18 },
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Package(){0x0013FFFF, 1, 0, 19 },
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Package(){0x0013FFFF, 2, 0, 16 },
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/* Package(){0x00140000, 0, 0, 16 }, */
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/* Package(){0x00130004, 2, 0, 18 }, */
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/* Package(){0x00130005, 3, 0, 19 }, */
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Package(){0x0013FFFF, 3, 0, 17 },
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/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
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Package(){0x0014FFFF, 0, 0, 16 },
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Package(){0x0014FFFF, 1, 0, 17 },
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Package(){0x0014FFFF, 2, 0, 18 },
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Package(){0x0014FFFF, 3, 0, 19 },
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/* Package(){0x00140004, 2, 0, 18 }, */
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/* Package(){0x00140004, 3, 0, 19 }, */
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/* Package(){0x00140005, 1, 0, 17 }, */
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/* Package(){0x00140006, 1, 0, 17 }, */
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})
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Name(PR1, Package(){
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/* Internal graphics - RS780 VGA, Bus1, Dev5 */
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Package(){0x0005FFFF, 0, INTA, 0 },
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Package(){0x0005FFFF, 1, INTB, 0 },
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Package(){0x0005FFFF, 2, INTC, 0 },
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Package(){0x0005FFFF, 3, INTD, 0 },
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Package(){0x0005FFFF, 0, INTC, 0 },
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Package(){0x0005FFFF, 1, INTD, 0 },
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Package(){0x0005FFFF, 2, INTA, 0 },
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Package(){0x0005FFFF, 3, INTB, 0 },
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})
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Name(APR1, Package(){
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/* Internal graphics - RS780 VGA, Bus1, Dev5 */
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Package(){0x0005FFFF, 0, 0, 18 },
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Package(){0x0005FFFF, 1, 0, 19 },
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/* Package(){0x0005FFFF, 2, 0, 20 }, */
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/* Package(){0x0005FFFF, 3, 0, 17 }, */
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Package(){0x0005FFFF, 2, 0, 16 },
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Package(){0x0005FFFF, 3, 0, 17 },
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})
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Name(PS2, Package(){
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@ -201,10 +227,10 @@ Scope(\_SB) {
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Name(PS4, Package(){
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/* PCIe slot - Hooked to PCIe slot 4 */
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Package(){0x0000FFFF, 0, INTA, 0 },
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Package(){0x0000FFFF, 1, INTB, 0 },
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Package(){0x0000FFFF, 2, INTC, 0 },
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Package(){0x0000FFFF, 3, INTD, 0 },
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Package(){0x0000FFFF, 0, INTD, 0 },
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Package(){0x0000FFFF, 1, INTA, 0 },
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Package(){0x0000FFFF, 2, INTB, 0 },
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Package(){0x0000FFFF, 3, INTC, 0 },
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})
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Name(APS4, Package(){
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@ -272,10 +298,10 @@ Scope(\_SB) {
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Name(APS9, Package(){
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/* PCIe slot - Hooked to PCIe slot 9 */
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Package(){0x0000FFFF, 0, 0, 17 },
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Package(){0x0000FFFF, 1, 0, 18 },
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Package(){0x0000FFFF, 2, 0, 19 },
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Package(){0x0000FFFF, 3, 0, 16 },
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Package(){0x0000FFFF, 0, 0, 19 },
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Package(){0x0000FFFF, 1, 0, 16 },
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Package(){0x0000FFFF, 2, 0, 17 },
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Package(){0x0000FFFF, 3, 0, 18 },
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})
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Name(PSa, Package(){
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/* PCIe slot - Hooked to PCIe slot 10 */
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@ -288,9 +314,9 @@ Scope(\_SB) {
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Name(APSa, Package(){
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/* PCIe slot - Hooked to PCIe slot 10 */
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Package(){0x0000FFFF, 0, 0, 18 },
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Package(){0x0000FFFF, 1, 0, 19 },
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Package(){0x0000FFFF, 2, 0, 16 },
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Package(){0x0000FFFF, 3, 0, 17 },
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Package(){0x0000FFFF, 1, 0, 16 },
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Package(){0x0000FFFF, 2, 0, 17 },
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Package(){0x0000FFFF, 3, 0, 18 },
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})
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Name(PCIB, Package(){
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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* Copyright (C) 2010-2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -20,13 +20,13 @@
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#include <console/console.h>
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#include <string.h>
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#include <arch/acpi.h>
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#include <arch/acpigen.h>
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#include <arch/ioapic.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/amd/amdfam10_sysconf.h>
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#include "mb_sysconf.h"
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#define DUMP_ACPI_TABLES 0
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@ -50,12 +50,33 @@ static void dump_mem(u32 start, u32 end)
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extern const unsigned char AmlCode[];
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extern const unsigned char AmlCode_ssdt[];
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#if CONFIG_ACPI_SSDTX_NUM >= 1
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extern const unsigned char AmlCode_ssdt2[];
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extern const unsigned char AmlCode_ssdt3[];
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extern const unsigned char AmlCode_ssdt4[];
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extern const unsigned char AmlCode_ssdt5[];
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#endif
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unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
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{
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int lens;
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msr_t msr;
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char pscope[] = "\\_SB.PCI0";
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lens = acpigen_write_scope(pscope);
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msr = rdmsr(TOP_MEM);
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lens += acpigen_write_name_dword("TOM1", msr.lo);
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msr = rdmsr(TOP_MEM2);
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/*
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* Since XP only implements parts of ACPI 2.0, we can't use a qword
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* here.
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* See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
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* slide 22ff.
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* Shift value right by 20 bit to make it fit into 32bit,
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* giving us 1MB granularity and a limit of almost 4Exabyte of memory.
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*/
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lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
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acpigen_patch_len(lens - 1);
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/* TODO: More HT and other tables need to go into this table generation.
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* This should also be moved out to the silicon level if it can.
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*/
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return (unsigned long) (acpigen_get_current());
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}
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unsigned long acpi_fill_mcfg(unsigned long current)
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{
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@ -69,8 +90,8 @@ unsigned long acpi_fill_madt(unsigned long current)
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current = acpi_create_madt_lapics(current);
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/* Write SB700 IOAPIC, only one */
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
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IO_APIC_ADDR, 0);
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
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CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 0, 2, 0);
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@ -101,11 +122,6 @@ unsigned long write_acpi_tables(unsigned long start)
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acpi_facs_t *facs;
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acpi_header_t *dsdt;
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acpi_header_t *ssdt;
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#if CONFIG_ACPI_SSDTX_NUM >= 1
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acpi_header_t *ssdtx;
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void *p;
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int i;
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#endif
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get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
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@ -127,6 +143,31 @@ unsigned long write_acpi_tables(unsigned long start)
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acpi_write_rsdp(rsdp, rsdt, NULL);
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acpi_write_rsdt(rsdt);
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/* DSDT */
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current = ( current + 0x07) & -0x08;
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printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
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dsdt = (acpi_header_t *)current; // it will used by fadt
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memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
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current += dsdt->length;
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memcpy(dsdt, &AmlCode, dsdt->length);
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printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
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/* FACS */ // it needs 64 bit alignment
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current = ( current + 0x07) & -0x08;
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printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
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facs = (acpi_facs_t *) current; // it will be used by fadt
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current += sizeof(acpi_facs_t);
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acpi_create_facs(facs);
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/* FADT */
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current = ( current + 0x07) & -0x08;
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printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
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fadt = (acpi_fadt_t *) current;
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current += sizeof(acpi_fadt_t);
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acpi_create_fadt(fadt, facs, dsdt);
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acpi_add_table(rsdp, fadt);
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/*
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* We explicitly add these tables later on:
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*/
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@ -162,87 +203,13 @@ unsigned long write_acpi_tables(unsigned long start)
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acpi_add_table(rsdp, slit);
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/* SSDT */
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current = ( current + 0x0f) & -0x10;
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printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
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ssdt = (acpi_header_t *)current;
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memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
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current = ( current + 0x0f) & -0x10;
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printk(BIOS_DEBUG, "ACPI: * coreboot PSTATE/TOM SSDT at %lx\n", current);
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ssdt = (acpi_header_t *) current;
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acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
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current += ssdt->length;
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memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
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//Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c
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update_ssdt((void*)ssdt);
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/* recalculate checksum */
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ssdt->checksum = 0;
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ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
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acpi_add_table(rsdp,ssdt);
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printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
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current = acpi_add_ssdt_pstates(rsdp, current);
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#if CONFIG_ACPI_SSDTX_NUM >= 1
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/* same htio, but different position? We may have to copy,
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change HCIN, and recalculate the checknum and add_table */
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for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink
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if((sysconf.pci1234[i] & 1) != 1 ) continue;
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u8 c;
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if (i < 7) {
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c = (u8) ('4' + i - 1);
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} else {
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c = (u8) ('A' + i - 1 - 6);
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}
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current = ( current + 0x07) & -0x08;
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printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt
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ssdtx = (acpi_header_t *)current;
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switch (sysconf.hcid[i]) {
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case 1:
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p = &AmlCode_ssdt2;
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break;
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case 2:
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p = &AmlCode_ssdt3;
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break;
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case 3: /* 8131 */
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p = &AmlCode_ssdt4;
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break;
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default:
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/* HTX no io apic */
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p = &AmlCode_ssdt5;
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break;
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}
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memcpy(ssdtx, p, sizeof(acpi_header_t));
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current += ssdtx->length;
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memcpy(ssdtx, p, ssdtx->length);
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update_ssdtx((void *)ssdtx, i);
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ssdtx->checksum = 0;
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ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length);
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acpi_add_table(rsdp, ssdtx);
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}
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#endif
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/* DSDT */
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current = ( current + 0x07) & -0x08;
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printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
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dsdt = (acpi_header_t *)current; // it will used by fadt
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memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
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current += dsdt->length;
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memcpy(dsdt, &AmlCode, dsdt->length);
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printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
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/* FACS */ // it needs 64 bit alignment
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current = ( current + 0x07) & -0x08;
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printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
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facs = (acpi_facs_t *) current; // it will be used by fadt
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current += sizeof(acpi_facs_t);
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acpi_create_facs(facs);
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/* FADT */
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current = ( current + 0x07) & -0x08;
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printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
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fadt = (acpi_fadt_t *) current;
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current += sizeof(acpi_fadt_t);
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acpi_create_fadt(fadt, facs, dsdt);
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acpi_add_table(rsdp, fadt);
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#if DUMP_ACPI_TABLES == 1
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printk(BIOS_DEBUG, "rsdp\n");
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@ -36,7 +36,7 @@ DefinitionBlock (
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Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
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Name(PBLN, 0x0) /* Length of BIOS area */
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Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
|
||||
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
|
||||
Name(HPBA, 0xFED00000) /* Base address of HPET table */
|
||||
|
||||
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
|
||||
|
|
@ -1168,7 +1168,7 @@ DefinitionBlock (
|
|||
/* Note: Only need HID on Primary Bus */
|
||||
Device(PCI0) {
|
||||
External (TOM1)
|
||||
External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
|
||||
External (TOM2)
|
||||
Name(_HID, EISAID("PNP0A03"))
|
||||
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
|
||||
Method(_BBN, 0) { /* Bus number = 0 */
|
||||
|
|
@ -1421,7 +1421,7 @@ DefinitionBlock (
|
|||
IRQNoFlags(){13}
|
||||
})
|
||||
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
|
||||
|
||||
#if 0 /* defined by HPET table? */
|
||||
Device(HPTM) {
|
||||
Name(_HID,EISAID("PNP0103"))
|
||||
Name(CRS,ResourceTemplate() {
|
||||
|
|
@ -1436,6 +1436,7 @@ DefinitionBlock (
|
|||
Return(CRS)
|
||||
}
|
||||
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
|
||||
#endif
|
||||
} /* end LIBR */
|
||||
|
||||
Device(HPBR) {
|
||||
|
|
@ -1450,7 +1451,7 @@ DefinitionBlock (
|
|||
Name(_ADR, 0x00140006)
|
||||
} /* end Ac97modem */
|
||||
|
||||
/* SIO Support */
|
||||
/* f71859 Support */
|
||||
OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
|
||||
Field (IOID, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
|
|
@ -1546,6 +1547,7 @@ DefinitionBlock (
|
|||
|
||||
Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
|
||||
Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
|
||||
#if 0
|
||||
Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
|
||||
Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
|
||||
|
||||
|
|
@ -1585,12 +1587,14 @@ DefinitionBlock (
|
|||
,,
|
||||
PEBM
|
||||
)
|
||||
|
||||
#endif
|
||||
/* memory space for PCI BARs below 4GB */
|
||||
Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
|
||||
}) /* End Name(_SB.PCI0.CRES) */
|
||||
|
||||
Method(_CRS, 0) {
|
||||
/* DBGO("\\_SB\\PCI0\\_CRS\n") */
|
||||
|
||||
#if 0
|
||||
CreateDWordField(CRES, ^EMM1._BAS, EM1B)
|
||||
CreateDWordField(CRES, ^EMM1._LEN, EM1L)
|
||||
CreateDWordField(CRES, ^DMLO._BAS, DMLB)
|
||||
|
|
@ -1614,8 +1618,7 @@ DefinitionBlock (
|
|||
/*
|
||||
* If(LNotEqual(TOM2, 0x00000000)){
|
||||
* Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
|
||||
* ShiftLeft(TOM2, 20, Local0)
|
||||
* Subtract(Local0, 0x100000000, DMHL)
|
||||
* Subtract(TOM2, 0x100000000, DMHL)
|
||||
* }
|
||||
*/
|
||||
|
||||
|
|
@ -1628,6 +1631,21 @@ DefinitionBlock (
|
|||
ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
|
||||
Store(PBLN,EBML)
|
||||
}
|
||||
#endif
|
||||
CreateDWordField(CRES, ^MMIO._BAS, MM1B)
|
||||
CreateDWordField(CRES, ^MMIO._LEN, MM1L)
|
||||
/*
|
||||
* Declare memory between TOM1 and 4GB as available
|
||||
* for PCI MMIO.
|
||||
* Use ShiftLeft to avoid 64bit constant (for XP).
|
||||
* This will work even if the OS does 32bit arithmetic, as
|
||||
* 32bit (0x00000000 - TOM1) will wrap and give the same
|
||||
* result as 64bit (0x100000000 - TOM1).
|
||||
*/
|
||||
Store(TOM1, MM1B)
|
||||
ShiftLeft(0x10000000, 4, Local0)
|
||||
Subtract(Local0, TOM1, Local0)
|
||||
Store(Local0, MM1L)
|
||||
|
||||
Return(CRES) /* note to change the Name buffer */
|
||||
} /* end of Method(_SB.PCI0._CRS) */
|
||||
|
|
|
|||
Loading…
Reference in New Issue