Convert AOpen DXPL Plus mainboard to CAR
Tested on real hardware, mainboard with dual Xeon P4 HT CPUs requires cache-as-ram init code with AP SIPI protocol. Also enable 2nd CPU and PATA and clean-up Kconfig and ACPI. Change-Id: I415482f3af22df79d82492c49aed83549f29aa56 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/886 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kyösti Mälkki
Patrick Georgi
parent
eb59636cc5
commit
3aff1a3208
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@ -8,8 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select SOUTHBRIDGE_INTEL_I82870
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select SOUTHBRIDGE_INTEL_I82801DX
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select SUPERIO_SMSC_LPC47M10X
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select ROMCC
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select HAVE_HARD_RESET
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# select HAVE_PIRQ_TABLE
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# select PIRQ_ROUTE
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select UDELAY_TSC
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@ -24,14 +22,6 @@ config MAINBOARD_PART_NUMBER
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string
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default "DXPL Plus-U"
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config DCACHE_RAM_BASE
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hex
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default 0xcf000
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config DCACHE_RAM_SIZE
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hex
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default 0x1000
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config IRQ_SLOT_COUNT
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int
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default 12
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@ -40,18 +30,10 @@ config BOARD_HAS_FADT
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bool
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default y
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config LOGICAL_CPUS
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bool
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default n
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config MAX_CPUS
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int
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default 4
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config MAX_PHYSICAL_CPUS
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int
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default 2
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config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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hex
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default 0x0
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@ -44,8 +44,8 @@ Name (PBRS, ResourceTemplate ()
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/* Top Of Lowmemory to IOAPIC */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
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0x00000000, 0x02000000, 0xFEBFFFFF,
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0x00000000, 0xFCC00000, ,, _Y08, AddressRangeMemory, TypeStatic)
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0x00000000, 0x00000000, 0xFEBFFFFF,
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0x00000000, IO_APIC_ADDR, ,, _Y08, AddressRangeMemory, TypeStatic)
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})
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@ -54,11 +54,13 @@ Method (_CRS, 0, NotSerialized)
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/* Top Of Lowmemory to IOAPIC */
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CreateDWordField (PBRS, \_SB.PCI0._Y08._MIN, MEML)
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CreateDWordField (PBRS, \_SB.PCI0._Y08._MAX, MEMH)
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CreateDWordField (PBRS, \_SB.PCI0._Y08._LEN, LENM)
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And (\_SB.PCI0.TOLM, 0xF800, Local1)
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ShiftRight (Local1, 0x04, Local1)
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ShiftLeft (Local1, 0x14, MEML)
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Subtract (0xFEC00000, MEML, LENM)
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Subtract (IO_APIC_ADDR, 0x01, MEMH)
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Subtract (IO_APIC_ADDR, MEML, LENM)
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Return (PBRS)
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}
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@ -96,7 +96,7 @@ Device (ICH0)
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Name (MSBF, ResourceTemplate ()
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{
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/* IOAPIC 0 */
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Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000,)
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Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000,)
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IO (Decode16, 0x0, 0x0, 0x80, 0x0, PMIO)
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IO (Decode16, 0x0, 0x0, 0x40, 0x0, GPIO)
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@ -24,6 +24,7 @@ chip northbridge/intel/e7505
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device lapic_cluster 0 on
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chip cpu/intel/socket_mPGA604
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device lapic 0 on end
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device lapic 6 on end
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end
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end
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@ -79,6 +80,8 @@ chip northbridge/intel/e7505
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end
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end
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device pci 1f.1 on end # IDE
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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device pci 1f.3 on end # SMBus
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device pci 1f.5 on end # AC97 Audio
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device pci 1f.6 off end # AC97 Modem
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@ -17,6 +17,8 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/ioapic.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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@ -27,6 +27,8 @@
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#include <stdlib.h>
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#include <pc80/mc146818rtc.h>
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#include <console/console.h>
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#include <cpu/x86/bist.h>
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#include <spd.h>
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#include "southbridge/intel/i82801dx/i82801dx.h"
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#include "southbridge/intel/i82801dx/early_smbus.c"
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@ -35,13 +37,6 @@
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#include "northbridge/intel/e7505/debug.c"
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#include "superio/smsc/lpc47m10x/early_serial.c"
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#if !CONFIG_CACHE_AS_RAM
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "cpu/x86/mtrr/earlymtrr.c"
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#endif
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#include "cpu/x86/bist.h"
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#include <spd.h>
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#define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1)
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@ -50,21 +45,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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return smbus_read_byte(device, address);
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}
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/* Cache-As-Ram compiles for this board, but with the CPUs I have,
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* it halts on boot while in Local Apic ID negotiation.
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*/
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#if CONFIG_CACHE_AS_RAM
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#define BOARD_MAIN(x) void main(x)
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#define early_mtrr_init() do {} while (0)
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#else
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#define BOARD_MAIN(x) static void main(x)
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#endif
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#include "northbridge/intel/e7505/raminit.c"
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// This function MUST appear last (ROMCC limitation)
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BOARD_MAIN(unsigned long bist)
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void main(unsigned long bist)
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{
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static const struct mem_controller memctrl[] = {
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{
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@ -75,12 +58,6 @@ BOARD_MAIN(unsigned long bist)
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},
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};
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if (bist == 0) {
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// Skip this if there was a built in self test failure
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early_mtrr_init();
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enable_lapic();
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}
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// Get the serial port running and print a welcome banner
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lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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@ -94,8 +71,5 @@ BOARD_MAIN(unsigned long bist)
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sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
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}
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// NOTE: ROMCC dies with an internal compiler error
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// if the following line is removed.
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print_debug("SDRAM is up.\r\n");
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print_debug("SDRAM is up.\n");
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}
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