compiles.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2004-08-24 22:27:55 +00:00
parent 74bfa2c8b2
commit 3b0096313a
6 changed files with 13 additions and 11 deletions

View File

@ -210,7 +210,7 @@ mainboardinit ./auto.inc
dir /pc80
config chip.h
northbridge intel/855pm "855pm"
northbridge intel/i855pm "i855pm"
# pci 0:0.0
# pci 0:1.0
southbridge intel/i82801dbm "i82801dbm"
@ -224,9 +224,6 @@ northbridge intel/855pm "855pm"
# pci 0:12.0
register "enable_usb" = "0"
register "enable_native_ide" = "0"
register "enable_com_ports" = "1"
register "enable_keyboard" = "0"
register "enable_nvram" = "1"
end
end

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@ -13,6 +13,8 @@
#include "northbridge/via/vt8601/raminit.h"
#include "cpu/p6/earlymtrr.c"
#include "southbridge/intel/i82801dbm/i82801dbm_early_smbus.c"
/*
*/
void udelay(int usecs)

View File

@ -1,13 +1,15 @@
#ifndef I82801ER_H
#define I82801ER_H
struct southbridge_intel_i82801er_config
struct southbridge_intel_i82801dbm_config
{
int enable_usb;
int enable_native_ide;
};
struct chip_control;
extern struct chip_control southbridge_intel_i82801er_control;
extern struct chip_control southbridge_intel_i82801dbm_control;
extern void i82801er_enable(device_t dev);
extern void i82801dbm_enable(device_t dev);
/*
000 = Non-combined. P0 is primary master. P1 is secondary master.
@ -78,4 +80,4 @@ channel disabled.
*/
#define SMBUS_TIMEOUT (100*1000)
#endif /* I82801ER_H */
#endif /* I82801DBM_H */

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@ -11,7 +11,7 @@ static void sata_init(struct device *dev)
uint16_t word;
uint8_t byte;
int enable_c=1, enable_d=1;
int i;
// int i;
//Enable Serial ATA port
byte = pci_read_config8(dev,0x90);

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@ -7,9 +7,10 @@
static void usb_init(struct device *dev)
{
uint32_t cmd;
#if 0
uint32_t cmd;
printk_debug("USB: Setting up controller.. ");
cmd = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND,