compiles.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -210,7 +210,7 @@ mainboardinit ./auto.inc
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dir /pc80
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config chip.h
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northbridge intel/855pm "855pm"
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northbridge intel/i855pm "i855pm"
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# pci 0:0.0
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# pci 0:1.0
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southbridge intel/i82801dbm "i82801dbm"
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@ -224,9 +224,6 @@ northbridge intel/855pm "855pm"
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# pci 0:12.0
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register "enable_usb" = "0"
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register "enable_native_ide" = "0"
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register "enable_com_ports" = "1"
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register "enable_keyboard" = "0"
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register "enable_nvram" = "1"
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end
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end
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@ -13,6 +13,8 @@
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#include "northbridge/via/vt8601/raminit.h"
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#include "cpu/p6/earlymtrr.c"
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#include "southbridge/intel/i82801dbm/i82801dbm_early_smbus.c"
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/*
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*/
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void udelay(int usecs)
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@ -1,13 +1,15 @@
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#ifndef I82801ER_H
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#define I82801ER_H
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struct southbridge_intel_i82801er_config
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struct southbridge_intel_i82801dbm_config
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{
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int enable_usb;
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int enable_native_ide;
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};
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struct chip_control;
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extern struct chip_control southbridge_intel_i82801er_control;
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extern struct chip_control southbridge_intel_i82801dbm_control;
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extern void i82801er_enable(device_t dev);
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extern void i82801dbm_enable(device_t dev);
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/*
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000 = Non-combined. P0 is primary master. P1 is secondary master.
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@ -78,4 +80,4 @@ channel disabled.
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*/
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#define SMBUS_TIMEOUT (100*1000)
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#endif /* I82801ER_H */
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#endif /* I82801DBM_H */
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@ -11,7 +11,7 @@ static void sata_init(struct device *dev)
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uint16_t word;
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uint8_t byte;
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int enable_c=1, enable_d=1;
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int i;
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// int i;
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//Enable Serial ATA port
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byte = pci_read_config8(dev,0x90);
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@ -7,9 +7,10 @@
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static void usb_init(struct device *dev)
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{
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uint32_t cmd;
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#if 0
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uint32_t cmd;
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printk_debug("USB: Setting up controller.. ");
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cmd = pci_read_config32(dev, PCI_COMMAND);
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pci_write_config32(dev, PCI_COMMAND,
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