GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/facebook/monolith/devicetree: Use comma separated list for arrays 

In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.

Don't convert the settings for PCIe root ports as they will be moved
into the devicetree to their related root ports at some later point.

While on it, remove superfluous comments related to modified settings.

Change-Id: I19af8c6b1167af793eb18b000fd93ec409385587
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78597
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This commit is contained in:
Felix Singer 2023-10-23 16:08:16 +02:00 committed by Felix Held
parent 21b5a9aff4
commit 3b01dd11cb
1 changed files with 14 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
src/mainboard/facebook/monolith/devicetree.cb
View File

@ -181,19 +181,21 @@ chip soc/intel/skylake
# Disable Aspm
register "pcie_rp_aspm[8]" = "AspmDisabled"
# USB 2.0 Enable all ports
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 2
register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # USB3_TYPE-A Port 1
register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB3_TYPE-A Port 2
register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 1
register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # M2 Port
register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # Audio board
register "usb2_ports" = "{
[0] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C Port 2 */
[1] = USB2_PORT_MID(OC1), /* USB3_TYPE-A Port 1 */
[2] = USB2_PORT_MID(OC1), /* USB3_TYPE-A Port 2 */
[3] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C Port 1 */
[4] = USB2_PORT_SHORT(OC_SKIP), /* M2 Port */
[6] = USB2_PORT_SHORT(OC_SKIP), /* Audio board */
}"
# USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C Port 2
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_TYPE-A Port 1
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_TYPE-A Port 2
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C Port 1
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 2 */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_TYPE-A Port 1 */
[2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_TYPE-A Port 2 */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 1 */
}"
register "SsicPortEnable" = "0"