baytrail: Add functions to peek at GPIO input values
- Add functions to peek at GPIO input pad values (need to be used from romstage for board ram_id GPIOs) - Modify UART GPIOs to use existing fn-assignment function TEST=Manual. Add debug print and verify that GPIO functions return input values. Also, verify UART still functions in romstage. BUG=chrome-os-partner:22865 Change-Id: Ib2e57631c127a592cfa20ab6e2184822424e9d77 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172189 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4870 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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@ -134,6 +134,10 @@
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#define PAD_VAL_OUTPUT_DISABLE (1 << 1)
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#define PAD_VAL_OUTPUT_ENABLE (0 << 1)
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/* pad_val[0] - Value */
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#define PAD_VAL_HIGH (1 << 0)
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#define PAD_VAL_LOW (0 << 0)
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/* pad_val reg power-on default varies by pad, and apparently can cause issues
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* if not set correctly, even if the pin isn't configured as GPIO. */
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#define PAD_VAL_DEFAULT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE)
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@ -247,6 +251,8 @@ struct soc_gpio_config* mainboard_get_gpios(void);
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/* Functions / defines for changing GPIOs in romstage */
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/* SCORE Pad definitions. */
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#define UART_RXD_PAD 82
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#define UART_TXD_PAD 83
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#define PCU_SMB_CLK_PAD 88
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#define PCU_SMB_DATA_PAD 90
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@ -282,4 +288,19 @@ static inline void ssus_select_func(int pad, int func)
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write32(pconf0_addr, reg);
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}
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/* These functions require that the input pad be configured as an input GPIO */
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static inline int score_get_gpio(int pad)
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{
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uint32_t val_addr = score_pconf0(pad) + PAD_VAL_REG;
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return read32(val_addr) & PAD_VAL_HIGH;
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}
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static inline int ssus_get_gpio(int pad)
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{
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uint32_t val_addr = ssus_pconf0(pad) + PAD_VAL_REG;
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return read32(val_addr) & PAD_VAL_HIGH;
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}
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#endif /* _BAYTRAIL_GPIO_H_ */
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@ -44,7 +44,7 @@ static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] =
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{ 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
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18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
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0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
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26, 51, 56, 54, 49, 55, 48, 47, 50, 58,
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26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
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52, 53, 59, 40 };
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/* GPIO bank descriptions */
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@ -32,8 +32,7 @@ void byt_config_com1_and_enable(void)
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reg = 1;
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pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg);
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/* Set up the pads to select the UART function. RXD and TXD are
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* 0x520 and 0x530, respectively. */
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write32(IO_BASE_ADDRESS + 0x520, read32(IO_BASE_ADDRESS + 0x520) | 1);
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write32(IO_BASE_ADDRESS + 0x530, read32(IO_BASE_ADDRESS + 0x530) | 1);
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/* Set up the pads to select the UART function */
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score_select_func(UART_RXD_PAD, 1);
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score_select_func(UART_TXD_PAD, 1);
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}
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