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baytrail: Add functions to peek at GPIO input values 

- Add functions to peek at GPIO input pad values (need to be used from
  romstage for board ram_id GPIOs)
- Modify UART GPIOs to use existing fn-assignment function

TEST=Manual. Add debug print and verify that GPIO functions return input
values. Also, verify UART still functions in romstage.
BUG=chrome-os-partner:22865

Change-Id: Ib2e57631c127a592cfa20ab6e2184822424e9d77
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172189
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4870
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Shawn Nematbakhsh 2013-10-08 11:31:21 -07:00 committed by Aaron Durbin
parent bb3ee83711
commit 3b036f7107
3 changed files with 25 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
src/soc/intel/baytrail/baytrail/gpio.h
View File

@ -134,6 +134,10 @@
#define PAD_VAL_OUTPUT_DISABLE (1 << 1) #define PAD_VAL_OUTPUT_DISABLE (1 << 1)
#define PAD_VAL_OUTPUT_ENABLE (0 << 1) #define PAD_VAL_OUTPUT_ENABLE (0 << 1)
/* pad_val[0] - Value */
#define PAD_VAL_HIGH (1 << 0)
#define PAD_VAL_LOW (0 << 0)
/* pad_val reg power-on default varies by pad, and apparently can cause issues /* pad_val reg power-on default varies by pad, and apparently can cause issues
* if not set correctly, even if the pin isn't configured as GPIO. */ * if not set correctly, even if the pin isn't configured as GPIO. */
#define PAD_VAL_DEFAULT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE) #define PAD_VAL_DEFAULT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE)
@ -247,6 +251,8 @@ struct soc_gpio_config* mainboard_get_gpios(void);
/* Functions / defines for changing GPIOs in romstage */ /* Functions / defines for changing GPIOs in romstage */
/* SCORE Pad definitions. */ /* SCORE Pad definitions. */
#define UART_RXD_PAD 82
#define UART_TXD_PAD 83
#define PCU_SMB_CLK_PAD 88 #define PCU_SMB_CLK_PAD 88
#define PCU_SMB_DATA_PAD 90 #define PCU_SMB_DATA_PAD 90
@ -282,4 +288,19 @@ static inline void ssus_select_func(int pad, int func)
write32(pconf0_addr, reg); write32(pconf0_addr, reg);
} }
/* These functions require that the input pad be configured as an input GPIO */
static inline int score_get_gpio(int pad)
{
uint32_t val_addr = score_pconf0(pad) + PAD_VAL_REG;
return read32(val_addr) & PAD_VAL_HIGH;
}
static inline int ssus_get_gpio(int pad)
{
uint32_t val_addr = ssus_pconf0(pad) + PAD_VAL_REG;
return read32(val_addr) & PAD_VAL_HIGH;
}
#endif /* _BAYTRAIL_GPIO_H_ */ #endif /* _BAYTRAIL_GPIO_H_ */

2
src/soc/intel/baytrail/gpio.c
View File

@ -44,7 +44,7 @@ static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] =
{ 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, { 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
18, 7, 11, 20, 17, 1, 8, 10, 19, 12, 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
0, 2, 23, 39, 28, 27, 22, 21, 24, 25, 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
26, 51, 56, 54, 49, 55, 48, 47, 50, 58, 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
52, 53, 59, 40 }; 52, 53, 59, 40 };
/* GPIO bank descriptions */ /* GPIO bank descriptions */

7
src/soc/intel/baytrail/romstage/uart.c
View File

@ -32,8 +32,7 @@ void byt_config_com1_and_enable(void)
reg = 1; reg = 1;
pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg);
/* Set up the pads to select the UART function. RXD and TXD are /* Set up the pads to select the UART function */
* 0x520 and 0x530, respectively. */ score_select_func(UART_RXD_PAD, 1);
write32(IO_BASE_ADDRESS + 0x520, read32(IO_BASE_ADDRESS + 0x520) | 1); score_select_func(UART_TXD_PAD, 1);
write32(IO_BASE_ADDRESS + 0x530, read32(IO_BASE_ADDRESS + 0x530) | 1);
} }