nb/intel/gm45: Use a common romstage
This moves a lot of the common romstage boilerplate code to a common location, while adding a few mainboard specific hooks. Another difference is that the settings for enable_igd and enable_peg are now based on the static devicetree settings. Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Arthur Heymans
Patrick Georgi
parent
1bde3124b4
commit
3b0eb602b9
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@ -16,15 +16,7 @@
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// __PRE_RAM__ means: use "unsigned" for device, not a struct.
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#include <stdint.h>
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#include <string.h>
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#include <arch/io.h>
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#include <arch/acpi.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/tsc.h>
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#include <cpu/intel/romstage.h>
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#include <cbmem.h>
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#include <romstage_handoff.h>
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#include <console/console.h>
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#include <southbridge/intel/i82801ix/i82801ix.h>
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#include <southbridge/intel/common/gpio.h>
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@ -33,7 +25,6 @@
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#include "dock.h"
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#define LPC_DEV PCI_DEV(0, 0x1f, 0)
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#define MCH_DEV PCI_DEV(0, 0, 0)
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static void hybrid_graphics_init(sysinfo_t *sysinfo)
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{
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@ -45,7 +36,9 @@ static void hybrid_graphics_init(sysinfo_t *sysinfo)
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sysinfo->enable_peg = peg;
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}
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static void early_lpc_setup(void)
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static int dock_err;
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void mb_setup_lpc(void)
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{
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/* Set up SuperIO LPC forwards */
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@ -59,99 +52,35 @@ static void early_lpc_setup(void)
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pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681);
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}
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void mainboard_romstage_entry(unsigned long bist)
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void mb_setup_superio(void)
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{
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sysinfo_t sysinfo;
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int s3resume = 0;
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int cbmem_initted;
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int err;
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u16 reg16;
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/* basic northbridge setup, including MMCONF BAR */
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gm45_early_init();
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if (bist == 0)
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enable_lapic();
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/* First, run everything needed for console output. */
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i82801ix_early_init();
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early_lpc_setup();
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/* Minimal setup to detect dock */
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err = pc87382_early();
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if (err == 0)
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dock_err = pc87382_early();
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if (dock_err == 0)
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dock_connect();
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}
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console_init();
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printk(BIOS_DEBUG, "running main(bist = %lu)\n", bist);
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void get_mb_spd_addrmap(u8 *spd_addrmap)
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{
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spd_addrmap[0] = 0x50;
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spd_addrmap[2] = 0x51;
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}
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/* Print dock info */
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if (err)
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void mb_pre_raminit_setup(sysinfo_t *sysinfo)
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{
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/* Console is not yet initialized in mb_setup_superio, so we print
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the dock information here */
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if (dock_err)
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printk(BIOS_ERR, "DOCK: Failed to init pc87382\n");
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else
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dock_info();
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reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3);
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pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16);
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if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) {
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printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
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gm45_early_reset();
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hybrid_graphics_init(sysinfo);
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}
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setup_pch_gpios(&mainboard_gpio_map);
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/* ASPM related setting, set early by original BIOS. */
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DMIBAR16(0x204) &= ~(3 << 10);
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/* Check for S3 resume. */
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const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04);
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if (((pm1_cnt >> 10) & 7) == 5) {
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if (acpi_s3_resume_allowed()) {
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printk(BIOS_DEBUG, "Resume from S3 detected.\n");
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s3resume = 1;
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/* Clear SLP_TYPE. This will break stage2 but
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* we care for that when we get there.
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*/
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outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04);
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} else {
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printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
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}
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}
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/* RAM initialization */
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enter_raminit_or_reset();
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memset(&sysinfo, 0, sizeof(sysinfo));
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sysinfo.spd_map[0] = 0x50;
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sysinfo.spd_map[2] = 0x51;
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get_gmch_info(&sysinfo);
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/* Configure graphic GPIOs.
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* Make sure there's a little delay between
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* setup_pch_gpios() and this call ! */
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hybrid_graphics_init(&sysinfo);
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raminit(&sysinfo, s3resume);
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const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN);
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/* Disable D4F0 (unknown signal controller). */
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pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000);
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init_pm(&sysinfo, 0);
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i82801ix_dmi_setup();
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gm45_late_init(sysinfo.stepping);
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i82801ix_dmi_poll_vc1();
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MCHBAR16(SSKPD_MCHBAR) = 0xCAFE;
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init_iommu();
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void mb_post_raminit_setup(void)
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{
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/* FIXME: make a proper SMBUS mux support. */
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/* Set the SMBUS mux to the eeprom */
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set_gpio(42, GPIO_LEVEL_LOW);
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cbmem_initted = !cbmem_recovery(s3resume);
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romstage_handoff_init(cbmem_initted && s3resume);
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printk(BIOS_SPEW, "exit main()\n");
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}
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@ -16,27 +16,15 @@
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// __PRE_RAM__ means: use "unsigned" for device, not a struct.
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#include <stdint.h>
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#include <string.h>
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#include <arch/io.h>
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#include <arch/acpi.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/tsc.h>
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#include <cpu/intel/romstage.h>
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#include <cbmem.h>
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#include <romstage_handoff.h>
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#include <console/console.h>
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#include <southbridge/intel/common/gpio.h>
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#include <southbridge/intel/i82801ix/i82801ix.h>
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#include <northbridge/intel/gm45/gm45.h>
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#define LPC_DEV PCI_DEV(0, 0x1f, 0)
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#define MCH_DEV PCI_DEV(0, 0, 0)
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static void early_lpc_setup(void)
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void mb_setup_lpc(void)
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{
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/* Set up SuperIO LPC forwards */
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/* Configure serial IRQs.*/
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pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0);
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/* Map COMa on 0x3f8, COMb on 0x2f8. */
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@ -47,82 +35,15 @@ static void early_lpc_setup(void)
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pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681);
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}
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void mainboard_romstage_entry(unsigned long bist)
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void get_mb_spd_addrmap(u8 *spd_addrmap)
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{
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sysinfo_t sysinfo;
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int s3resume = 0;
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int cbmem_initted;
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u16 reg16;
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/* basic northbridge setup, including MMCONF BAR */
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gm45_early_init();
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if (bist == 0)
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enable_lapic();
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/* First, run everything needed for console output. */
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i82801ix_early_init();
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early_lpc_setup();
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console_init();
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printk(BIOS_DEBUG, "running main(bist = %lu)\n", bist);
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reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3);
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pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16);
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if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) {
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printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
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gm45_early_reset();
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spd_addrmap[0] = 0x50;
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spd_addrmap[2] = 0x51;
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}
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setup_pch_gpios(&mainboard_gpio_map);
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/* ASPM related setting, set early by original BIOS. */
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DMIBAR16(0x204) &= ~(3 << 10);
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/* Check for S3 resume. */
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const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04);
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if (((pm1_cnt >> 10) & 7) == 5) {
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if (acpi_s3_resume_allowed()) {
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printk(BIOS_DEBUG, "Resume from S3 detected.\n");
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s3resume = 1;
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/* Clear SLP_TYPE. This will break stage2 but
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* we care for that when we get there.
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*/
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outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04);
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} else {
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printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
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}
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}
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/* RAM initialization */
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enter_raminit_or_reset();
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memset(&sysinfo, 0, sizeof(sysinfo));
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sysinfo.spd_map[0] = 0x50;
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sysinfo.spd_map[2] = 0x51;
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sysinfo.enable_igd = 1;
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sysinfo.enable_peg = 0;
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get_gmch_info(&sysinfo);
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raminit(&sysinfo, s3resume);
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const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN);
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/* Disable D4F0 (unknown signal controller). */
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pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000);
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init_pm(&sysinfo, 0);
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i82801ix_dmi_setup();
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gm45_late_init(sysinfo.stepping);
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i82801ix_dmi_poll_vc1();
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MCHBAR16(SSKPD_MCHBAR) = 0xCAFE;
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init_iommu();
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void mb_post_raminit_setup(void)
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{
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/* FIXME: make a proper SMBUS mux support. */
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/* Set the SMBUS mux to the eeprom */
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set_gpio(42, GPIO_LEVEL_LOW);
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cbmem_initted = !cbmem_recovery(s3resume);
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romstage_handoff_init(cbmem_initted && s3resume);
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printk(BIOS_SPEW, "exit main()\n");
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}
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@ -16,17 +16,7 @@
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/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */
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#include <stdint.h>
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#include <string.h>
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#include <arch/io.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/tsc.h>
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#include <cpu/intel/romstage.h>
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#include <arch/acpi.h>
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#include <cbmem.h>
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#include <romstage_handoff.h>
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#include <console/console.h>
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#include <southbridge/intel/common/gpio.h>
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#include <southbridge/intel/i82801ix/i82801ix.h>
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#include <northbridge/intel/gm45/gm45.h>
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@ -35,7 +25,7 @@
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#define LPC_DEV PCI_DEV(0, 0x1f, 0)
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#define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1)
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static void early_lpc_setup(void)
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void mb_setup_lpc(void)
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{
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/* Set up SuperIO LPC forwards */
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@ -47,7 +37,7 @@ static void early_lpc_setup(void)
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pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3c03);
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}
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static void default_superio_gpio_setup(void)
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void mb_setup_superio(void)
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{
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/* Original settings:
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idx 30 31 32 33 34 35 36 37 38 39
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@ -87,81 +77,12 @@ static void default_superio_gpio_setup(void)
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/* Set GPIO output values: */
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outb(0x88, 0x600 + 0xb + 3); /* GP30 - GP37 */
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outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */
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}
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void mainboard_romstage_entry(unsigned long bist)
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{
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sysinfo_t sysinfo;
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int s3resume = 0;
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int cbmem_initted;
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u16 reg16;
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/* basic northbridge setup, including MMCONF BAR */
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gm45_early_init();
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if (bist == 0)
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enable_lapic();
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/* First, run everything needed for console output. */
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i82801ix_early_init();
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early_lpc_setup();
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default_superio_gpio_setup();
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lpc47n227_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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printk(BIOS_DEBUG, "running main(bist = %lu)\n", bist);
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reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3);
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pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16);
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if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) {
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printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
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gm45_early_reset();
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}
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setup_pch_gpios(&mainboard_gpio_map);
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/* ASPM related setting, set early by original BIOS. */
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DMIBAR16(0x204) &= ~(3 << 10);
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/* Check for S3 resume. */
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const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04);
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if (((pm1_cnt >> 10) & 7) == 5) {
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if (acpi_s3_resume_allowed()) {
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printk(BIOS_DEBUG, "Resume from S3 detected.\n");
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s3resume = 1;
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/* Clear SLP_TYPE. This will break stage2 but
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* we care for that when we get there.
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*/
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outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04);
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} else {
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printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
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}
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}
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/* RAM initialization */
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enter_raminit_or_reset();
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memset(&sysinfo, 0, sizeof(sysinfo));
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get_gmch_info(&sysinfo);
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sysinfo.spd_map[0] = 0x50;
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sysinfo.spd_map[1] = 0;
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sysinfo.spd_map[2] = 0x52;
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sysinfo.spd_map[3] = 0;
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sysinfo.enable_igd = 1;
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sysinfo.enable_peg = 0;
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raminit(&sysinfo, s3resume);
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init_pm(&sysinfo, 1);
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i82801ix_dmi_setup();
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gm45_late_init(sysinfo.stepping);
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i82801ix_dmi_poll_vc1();
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MCHBAR16(SSKPD_MCHBAR) = 0xCAFE;
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init_iommu();
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cbmem_initted = !cbmem_recovery(s3resume);
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romstage_handoff_init(cbmem_initted && s3resume);
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printk(BIOS_SPEW, "exit main()\n");
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void get_mb_spd_addrmap(u8 *spd_addrmap)
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{
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spd_addrmap[0] = 0x50;
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spd_addrmap[2] = 0x52;
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}
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@ -27,6 +27,7 @@ romstage-y += igd.c
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romstage-y += pm.c
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romstage-y += ram_calc.c
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romstage-y += iommu.c
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romstage-y += romstage.c
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ramstage-y += acpi.c
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@ -436,6 +436,13 @@ u32 decode_tseg_size(u8 esmramc);
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void init_iommu(void);
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/* romstage mainboard hookups */
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void mb_setup_lpc(void);
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void mb_setup_superio(void); /* optional */
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void get_mb_spd_addrmap(u8 spd_addrmap[4]);
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void mb_pre_raminit_setup(sysinfo_t *); /* optional */
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void mb_post_raminit_setup(void); /* optional */
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struct blc_pwm_t {
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char ascii_string[13];
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int pwm_freq; /* In Hz */
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@ -0,0 +1,135 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2010 coresystems GmbH
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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* Copyright (C) 2014 Vladimir Serbinenko
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*
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* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <cbmem.h>
|
||||
#include <romstage_handoff.h>
|
||||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <cpu/intel/romstage.h>
|
||||
#include <northbridge/intel/gm45/gm45.h>
|
||||
#include <southbridge/intel/i82801ix/i82801ix.h>
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
|
||||
#define MCH_DEV PCI_DEV(0, 0, 0)
|
||||
|
||||
void __weak mb_setup_superio(void)
|
||||
{
|
||||
}
|
||||
|
||||
void __weak mb_pre_raminit_setup(sysinfo_t *sysinfo)
|
||||
{
|
||||
}
|
||||
|
||||
void __weak mb_post_raminit_setup(void)
|
||||
{
|
||||
}
|
||||
|
||||
/* Platform has no romstage entry point under mainboard directory,
|
||||
* so this one is named with prefix mainboard.
|
||||
*/
|
||||
void mainboard_romstage_entry(unsigned long bist)
|
||||
{
|
||||
sysinfo_t sysinfo;
|
||||
int s3resume = 0;
|
||||
int cbmem_initted;
|
||||
u16 reg16;
|
||||
|
||||
/* basic northbridge setup, including MMCONF BAR */
|
||||
gm45_early_init();
|
||||
|
||||
if (bist == 0)
|
||||
enable_lapic();
|
||||
|
||||
/* First, run everything needed for console output. */
|
||||
i82801ix_early_init();
|
||||
setup_pch_gpios(&mainboard_gpio_map);
|
||||
|
||||
mb_setup_lpc();
|
||||
|
||||
mb_setup_superio();
|
||||
|
||||
console_init();
|
||||
report_bist_failure(bist);
|
||||
|
||||
reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3);
|
||||
pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16);
|
||||
if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) {
|
||||
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
|
||||
gm45_early_reset();
|
||||
}
|
||||
|
||||
/* ASPM related setting, set early by original BIOS. */
|
||||
DMIBAR16(0x204) &= ~(3 << 10);
|
||||
|
||||
/* Check for S3 resume. */
|
||||
const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04);
|
||||
if (((pm1_cnt >> 10) & 7) == 5) {
|
||||
if (acpi_s3_resume_allowed()) {
|
||||
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
|
||||
s3resume = 1;
|
||||
/* Clear SLP_TYPE. This will break stage2 but
|
||||
* we care for that when we get there.
|
||||
*/
|
||||
outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* RAM initialization */
|
||||
enter_raminit_or_reset();
|
||||
memset(&sysinfo, 0, sizeof(sysinfo));
|
||||
get_mb_spd_addrmap(sysinfo.spd_map);
|
||||
const struct device *dev;
|
||||
dev = pcidev_on_root(2, 0);
|
||||
if (dev)
|
||||
sysinfo.enable_igd = dev->enabled;
|
||||
dev = pcidev_on_root(1, 0);
|
||||
if (dev)
|
||||
sysinfo.enable_peg = dev->enabled;
|
||||
get_gmch_info(&sysinfo);
|
||||
|
||||
mb_pre_raminit_setup(&sysinfo);
|
||||
|
||||
raminit(&sysinfo, s3resume);
|
||||
|
||||
mb_post_raminit_setup();
|
||||
|
||||
const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN);
|
||||
/* Disable D4F0 (unknown signal controller). */
|
||||
pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000);
|
||||
|
||||
init_pm(&sysinfo, 0);
|
||||
|
||||
i82801ix_dmi_setup();
|
||||
gm45_late_init(sysinfo.stepping);
|
||||
i82801ix_dmi_poll_vc1();
|
||||
|
||||
MCHBAR16(SSKPD_MCHBAR) = 0xCAFE;
|
||||
|
||||
init_iommu();
|
||||
|
||||
cbmem_initted = !cbmem_recovery(s3resume);
|
||||
|
||||
romstage_handoff_init(cbmem_initted && s3resume);
|
||||
|
||||
printk(BIOS_SPEW, "exit main()\n");
|
||||
}
|
||||
Loading…
Reference in New Issue