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mb/google/hatch: Enable LPC/eSPI controller 

Enable LPC/eSPI controller(D31:F0). EC would be using
eSPI interface, since the strap GPP_C5 is pulled up.

BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot

Change-Id: Ia4baf80a775ba8898055f82e80dc583e65c4ed0b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This commit is contained in:
Aamir Bohra 2018-12-25 12:00:39 +05:30 committed by Subrata Banik
parent afc63844e2
commit 3b1a42f95d
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
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@ -96,7 +96,7 @@ chip soc/intel/cannonlake
end end
end # GSPI #0 end # GSPI #0
device pci 1e.3 off end # GSPI #1 device pci 1e.3 off end # GSPI #1
device pci 1f.0 off end # LPC/eSPI device pci 1f.0 on end # LPC/eSPI
device pci 1f.1 off end # P2SB device pci 1f.1 off end # P2SB
device pci 1f.2 off end # Power Management Controller device pci 1f.2 off end # Power Management Controller
device pci 1f.3 off end # Intel HDA device pci 1f.3 off end # Intel HDA