mb/google/hatch: Enable LPC/eSPI controller
Enable LPC/eSPI controller(D31:F0). EC would be using eSPI interface, since the strap GPP_C5 is pulled up. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: Ia4baf80a775ba8898055f82e80dc583e65c4ed0b Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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@ -96,7 +96,7 @@ chip soc/intel/cannonlake
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end
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end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1f.0 off end # LPC/eSPI
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device pci 1f.0 on end # LPC/eSPI
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device pci 1f.1 off end # P2SB
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device pci 1f.2 off end # Power Management Controller
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device pci 1f.3 off end # Intel HDA
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