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mb/google/brya/var/marasov: Disable touch panel power for non-touch sku 

Disable touch panel power for non-touch sku by fw_config TOUCH field.

BUG=b:263452842
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I4736f94481512806377b733b26fdc7290046c555
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71691
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Frank Chu 2023-01-06 11:20:55 +08:00 committed by Eric Lai
parent ce6cdb3608
commit 3b23fa6092
3 changed files with 36 additions and 1 deletions
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1
src/mainboard/google/brya/variants/marasov/Makefile.inc
View File

@ -2,6 +2,7 @@
bootblock-y += gpio.c bootblock-y += gpio.c
romstage-y += gpio.c romstage-y += gpio.c
ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
romstage-y += memory.c romstage-y += memory.c

28
src/mainboard/google/brya/variants/marasov/fw_config.c Normal file
View File

@ -0,0 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootstate.h>
#include <console/console.h>
#include <fw_config.h>
#include <gpio.h>
static const struct pad_config touch_enable_pads[] = {
/* C0 : SMBCLK ==> EN_PP3300_TCHSCR */
PAD_CFG_GPO(GPP_C0, 1, DEEP),
};
static const struct pad_config touch_disable_pads[] = {
/* C0 : SMBCLK ==> NC */
PAD_NC(GPP_C0, NONE),
};
static void fw_config_handle(void *unused)
{
if (fw_config_probe(FW_CONFIG(TOUCH, TOUCH_ELAN0001))) {
printk(BIOS_INFO, "Configure Touch GPIO GPP_C0 to GPO_H.\n");
gpio_configure_pads(touch_enable_pads, ARRAY_SIZE(touch_enable_pads));
} else {
printk(BIOS_INFO, "Configure Touch GPIO GPP_C0 to NC.\n");
gpio_configure_pads(touch_disable_pads, ARRAY_SIZE(touch_disable_pads));
}
}
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);

8
src/mainboard/google/brya/variants/marasov/overridetree.cb
View File

@ -12,6 +12,10 @@ fw_config
option UFC_USB 0 option UFC_USB 0
option UFC_MIPI 1 option UFC_MIPI 1
end end
field TOUCH 5 5
option TOUCH_NONE 0
option TOUCH_ELAN0001 1
end
field STORAGE 30 31 field STORAGE 30 31
option STORAGE_UNKNOWN 0 option STORAGE_UNKNOWN 0
option STORAGE_NVME 1 option STORAGE_NVME 1
@ -163,7 +167,9 @@ chip soc/intel/alderlake
register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
register "stop_off_delay_ms" = "1" register "stop_off_delay_ms" = "1"
register "has_power_resource" = "1" register "has_power_resource" = "1"
device i2c 10 on end device i2c 10 on
probe TOUCH TOUCH_ELAN0001
end
end end
end #I2C3 end #I2C3
device ref i2c5 on device ref i2c5 on