mb/google/hades: Add variant device tree
Follow 03_16 schematic to add the device tree. BUG=b:272816611 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I85a05fec816954fd3408feccae84e0b9860ecdc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73838 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
This commit is contained in:
Eric Lai
parent
a5abcf2be3
commit
3b3012fa7d
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@ -351,6 +351,11 @@ config BOARD_GOOGLE_AURASH
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config BOARD_GOOGLE_HADES
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config BOARD_GOOGLE_HADES
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bool "-> Hades"
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bool "-> Hades"
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select BOARD_GOOGLE_BASEBOARD_HADES
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select BOARD_GOOGLE_BASEBOARD_HADES
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select DRIVERS_GENESYSLOGIC_GL9750
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select PCIEXP_SUPPORT_RESIZABLE_BARS
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select RT8168_GEN_ACPI_POWER_RESOURCE
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select RT8168_GET_MAC_FROM_VPD
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select RT8168_SET_LED_MODE
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config BOARD_GOOGLE_ULDREN
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config BOARD_GOOGLE_ULDREN
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bool "-> Uldren"
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bool "-> Uldren"
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@ -1,4 +1,366 @@
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chip soc/intel/alderlake
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chip soc/intel/alderlake
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| I2C0 | Audio |
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#| I2C1 | GPU |
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#| I2C2 | External graphic |
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#| I2C3 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| I2C5 | Trackpad |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 650,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 650,
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.fall_time_ns = 300,
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.data_hold_time_ns = 50,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 650,
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.fall_time_ns = 300,
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.data_hold_time_ns = 50,
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},
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.i2c[3] = {
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.early_init = 1,
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 600,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 650,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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}"
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register "tcc_offset" = "3" # TCC of 97
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register "sagv" = "SaGv_Disabled"
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C0
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register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2_C1
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # UCAM
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register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # Type-A Port A1
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register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A0
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port A1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0
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register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC2)" # Typc-C Port C1
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register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC1)" # Typc-C Port C0
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register "serial_io_i2c_mode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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}"
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device domain 0 on
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device domain 0 on
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device ref pcie4_0 on
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# Enable CPU PCIe RP 1 using CLKREQ 0 and CLKSRC 0
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_req = 0,
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.clk_src = 0,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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device pci 00.0 alias dgpu on end
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end
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device ref dtt on
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chip drivers/intel/dptf
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## sensor information
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register "options.tsr[0].desc" = ""DRAM""
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register "options.tsr[1].desc" = ""GPU""
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register "options.tsr[2].desc" = ""Charger""
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# TODO: below values are initial reference values only
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## Active Policy
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register "policies.active" = "{
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[0] = {
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.target = DPTF_CPU,
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.thresholds = {
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TEMP_PCT(85, 90),
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TEMP_PCT(80, 80),
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TEMP_PCT(75, 70),
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TEMP_PCT(70, 50),
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TEMP_PCT(65, 30),
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}
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},
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[1] = {
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.target = DPTF_TEMP_SENSOR_1,
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.thresholds = {
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TEMP_PCT(50, 90),
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TEMP_PCT(48, 70),
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TEMP_PCT(46, 60),
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TEMP_PCT(43, 40),
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TEMP_PCT(40, 30),
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}
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}
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}"
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## Passive Policy
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
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[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000),
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[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000),
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}"
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## Critical Policy
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 105, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 105, SHUTDOWN),
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[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 105, SHUTDOWN),
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}"
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 3000,
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.max_power = 15000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 200,
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},
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.pl2 = {
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.min_power = 55000,
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.max_power = 55000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 1000,
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}
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}"
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register "oem_data.oem_variables" = "{
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[0] = 0x0
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}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf" = "{
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[0] = { 255, 1700 },
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[1] = { 24, 1500 },
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[2] = { 16, 1000 },
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[3] = { 8, 500 }
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}"
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## Fan Performance Control (Percent, Speed, Noise, Power)
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register "controls.fan_perf" = "{
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[0] = { 90, 4700, 220, 2200, },
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[1] = { 80, 4500, 180, 1800, },
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[2] = { 70, 4300, 145, 1450, },
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[3] = { 60, 3700, 115, 1150, },
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[4] = { 50, 3300, 90, 900, },
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[5] = { 40, 3100, 55, 550, },
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[6] = { 30, 2800, 30, 300, },
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[7] = { 20, 2500, 15, 150, },
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[8] = { 10, 2300, 10, 100, },
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[9] = { 0, 0, 0, 50, }
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}"
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## Fan options
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register "options.fan.fine_grained_control" = "1"
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register "options.fan.step_size" = "2"
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device generic 0 alias dptf_policy on end
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end
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end
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
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end
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end
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device ref i2c0 on
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chip drivers/i2c/generic
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register "hid" = ""RTL5682""
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register "name" = ""RT58""
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register "desc" = ""Headset Codec""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
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# Set the jd_src to RT5668_JD1 for jack detection
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register "property_count" = "1"
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on end
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end
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end #I2C0
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device ref i2c1 on end # GPU
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device ref i2c2 on end # External GPU
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device ref i2c3 on
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chip drivers/i2c/tpm
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register "hid" = ""GOOG0005""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
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device i2c 50 on end
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end
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end
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device ref i2c5 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
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register "wake" = "GPE0_DW2_14"
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register "detect" = "1"
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device i2c 15 on end
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end
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end
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device ref pcie_rp3 on
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# Enable PCIE 3 using clk 4
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register "pch_pcie_rp[PCH_RP(3)]" = "{
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.clk_src = 4,
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.clk_req = 4,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip drivers/net
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register "customized_leds" = "0x05af"
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register "wake" = "GPE0_DW0_07"
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register "device_index" = "0"
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register "add_acpi_dma_property" = "true"
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device pci 00.0 on end
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end
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end #RTL8111H Ethernet NIC
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device ref pcie_rp4 off end
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device ref pcie_rp6 off end
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device ref pcie_rp7 off end
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device ref pcie_rp8 on
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
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register "srcclk_pin" = "3"
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device generic 0 on end
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end
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# Enable SD Card PCIE 8 using clk 3
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register "pch_pcie_rp[PCH_RP(8)]" = "{
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.clk_src = 3,
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.clk_req = 3,
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.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end #PCIE8 SD card
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device ref pcie_rp9 on
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# Enable NVMe PCIE 9 using clk 1
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register "pch_pcie_rp[PCH_RP(9)]" = "{
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.clk_src = 1,
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.clk_req = 1,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end #PCIE9-12 SSD
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device ref hda on
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chip drivers/generic/max98357a
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register "hid" = ""MX98360A""
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register "sdmode_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
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register "sdmode_delay" = "5"
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device generic 0 on end
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end
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end
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device ref pch_espi on
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chip ec/google/chromeec
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use conn0 as mux_conn[0]
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use conn1 as mux_conn[1]
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device pnp 0c09.0 on end
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end
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end
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device ref pmc hidden
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chip drivers/intel/pmc_mux
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device generic 0 on
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chip drivers/intel/pmc_mux/conn
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use usb2_port1 as usb2_port
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use tcss_usb3_port3 as usb3_port
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device generic 0 alias conn0 on end
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end
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chip drivers/intel/pmc_mux/conn
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use usb2_port3 as usb2_port
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use tcss_usb3_port1 as usb3_port
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device generic 1 alias conn1 on end
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end
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end
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end
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end
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device ref tcss_xhci on
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chip drivers/usb/acpi
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C1 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
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device ref tcss_usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
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device ref tcss_usb3_port3 on end
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end
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end
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end
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end
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device ref xhci on
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
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device ref usb2_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C1 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
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device ref usb2_port3 on end
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end
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chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 Camera""
|
||||||
|
register "type" = "UPC_TYPE_INTERNAL"
|
||||||
|
device ref usb2_port6 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 Type-A Port 1""
|
||||||
|
register "type" = "UPC_TYPE_A"
|
||||||
|
register "use_custom_pld" = "true"
|
||||||
|
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 2))"
|
||||||
|
device ref usb2_port8 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 Type-A Port 0""
|
||||||
|
register "type" = "UPC_TYPE_A"
|
||||||
|
register "use_custom_pld" = "true"
|
||||||
|
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
|
||||||
|
device ref usb2_port9 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 Bluetooth""
|
||||||
|
register "type" = "UPC_TYPE_INTERNAL"
|
||||||
|
register "reset_gpio" =
|
||||||
|
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
|
||||||
|
device ref usb2_port10 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB3 Type-A Port 1""
|
||||||
|
register "type" = "UPC_TYPE_USB3_A"
|
||||||
|
register "use_custom_pld" = "true"
|
||||||
|
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
|
||||||
|
device ref usb3_port1 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB3 Type-A Port 0""
|
||||||
|
register "type" = "UPC_TYPE_USB3_A"
|
||||||
|
register "use_custom_pld" = "true"
|
||||||
|
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 2))"
|
||||||
|
device ref usb3_port2 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue