mb/google/hades: Add variant device tree
Follow 03_16 schematic to add the device tree. BUG=b:272816611 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I85a05fec816954fd3408feccae84e0b9860ecdc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73838 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
This commit is contained in:
Eric Lai
parent
a5abcf2be3
commit
3b3012fa7d
|
|
@ -351,6 +351,11 @@ config BOARD_GOOGLE_AURASH
|
|||
config BOARD_GOOGLE_HADES
|
||||
bool "-> Hades"
|
||||
select BOARD_GOOGLE_BASEBOARD_HADES
|
||||
select DRIVERS_GENESYSLOGIC_GL9750
|
||||
select PCIEXP_SUPPORT_RESIZABLE_BARS
|
||||
select RT8168_GEN_ACPI_POWER_RESOURCE
|
||||
select RT8168_GET_MAC_FROM_VPD
|
||||
select RT8168_SET_LED_MODE
|
||||
|
||||
config BOARD_GOOGLE_ULDREN
|
||||
bool "-> Uldren"
|
||||
|
|
|
|||
|
|
@ -1,4 +1,366 @@
|
|||
chip soc/intel/alderlake
|
||||
# Intel Common SoC Config
|
||||
#+-------------------+---------------------------+
|
||||
#| Field | Value |
|
||||
#+-------------------+---------------------------+
|
||||
#| I2C0 | Audio |
|
||||
#| I2C1 | GPU |
|
||||
#| I2C2 | External graphic |
|
||||
#| I2C3 | cr50 TPM. Early init is |
|
||||
#| | required to set up a BAR |
|
||||
#| | for TPM communication |
|
||||
#| I2C5 | Trackpad |
|
||||
#+-------------------+---------------------------+
|
||||
register "common_soc_config" = "{
|
||||
.i2c[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 650,
|
||||
.fall_time_ns = 400,
|
||||
.data_hold_time_ns = 50,
|
||||
},
|
||||
.i2c[1] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 650,
|
||||
.fall_time_ns = 300,
|
||||
.data_hold_time_ns = 50,
|
||||
},
|
||||
.i2c[2] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 650,
|
||||
.fall_time_ns = 300,
|
||||
.data_hold_time_ns = 50,
|
||||
},
|
||||
.i2c[3] = {
|
||||
.early_init = 1,
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 600,
|
||||
.fall_time_ns = 400,
|
||||
.data_hold_time_ns = 50,
|
||||
},
|
||||
.i2c[5] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 650,
|
||||
.fall_time_ns = 400,
|
||||
.data_hold_time_ns = 50,
|
||||
},
|
||||
}"
|
||||
|
||||
register "tcc_offset" = "3" # TCC of 97
|
||||
register "sagv" = "SaGv_Disabled"
|
||||
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C0
|
||||
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2_C1
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # UCAM
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # Type-A Port A1
|
||||
register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A0
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port A1
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0
|
||||
|
||||
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC2)" # Typc-C Port C1
|
||||
register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC1)" # Typc-C Port C0
|
||||
|
||||
register "serial_io_i2c_mode" = "{
|
||||
[PchSerialIoIndexI2C0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C1] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C2] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C3] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C5] = PchSerialIoPci,
|
||||
}"
|
||||
|
||||
device domain 0 on
|
||||
device ref pcie4_0 on
|
||||
# Enable CPU PCIe RP 1 using CLKREQ 0 and CLKSRC 0
|
||||
register "cpu_pcie_rp[CPU_RP(1)]" = "{
|
||||
.clk_req = 0,
|
||||
.clk_src = 0,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
device pci 00.0 alias dgpu on end
|
||||
end
|
||||
device ref dtt on
|
||||
chip drivers/intel/dptf
|
||||
## sensor information
|
||||
register "options.tsr[0].desc" = ""DRAM""
|
||||
register "options.tsr[1].desc" = ""GPU""
|
||||
register "options.tsr[2].desc" = ""Charger""
|
||||
# TODO: below values are initial reference values only
|
||||
## Active Policy
|
||||
register "policies.active" = "{
|
||||
[0] = {
|
||||
.target = DPTF_CPU,
|
||||
.thresholds = {
|
||||
TEMP_PCT(85, 90),
|
||||
TEMP_PCT(80, 80),
|
||||
TEMP_PCT(75, 70),
|
||||
TEMP_PCT(70, 50),
|
||||
TEMP_PCT(65, 30),
|
||||
}
|
||||
},
|
||||
[1] = {
|
||||
.target = DPTF_TEMP_SENSOR_1,
|
||||
.thresholds = {
|
||||
TEMP_PCT(50, 90),
|
||||
TEMP_PCT(48, 70),
|
||||
TEMP_PCT(46, 60),
|
||||
TEMP_PCT(43, 40),
|
||||
TEMP_PCT(40, 30),
|
||||
}
|
||||
}
|
||||
}"
|
||||
## Passive Policy
|
||||
register "policies.passive" = "{
|
||||
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
|
||||
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
|
||||
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000),
|
||||
[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000),
|
||||
}"
|
||||
## Critical Policy
|
||||
register "policies.critical" = "{
|
||||
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
|
||||
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 105, SHUTDOWN),
|
||||
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 105, SHUTDOWN),
|
||||
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 105, SHUTDOWN),
|
||||
}"
|
||||
register "controls.power_limits" = "{
|
||||
.pl1 = {
|
||||
.min_power = 3000,
|
||||
.max_power = 15000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 200,
|
||||
},
|
||||
.pl2 = {
|
||||
.min_power = 55000,
|
||||
.max_power = 55000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 1000,
|
||||
}
|
||||
}"
|
||||
register "oem_data.oem_variables" = "{
|
||||
[0] = 0x0
|
||||
}"
|
||||
## Charger Performance Control (Control, mA)
|
||||
register "controls.charger_perf" = "{
|
||||
[0] = { 255, 1700 },
|
||||
[1] = { 24, 1500 },
|
||||
[2] = { 16, 1000 },
|
||||
[3] = { 8, 500 }
|
||||
}"
|
||||
## Fan Performance Control (Percent, Speed, Noise, Power)
|
||||
register "controls.fan_perf" = "{
|
||||
[0] = { 90, 4700, 220, 2200, },
|
||||
[1] = { 80, 4500, 180, 1800, },
|
||||
[2] = { 70, 4300, 145, 1450, },
|
||||
[3] = { 60, 3700, 115, 1150, },
|
||||
[4] = { 50, 3300, 90, 900, },
|
||||
[5] = { 40, 3100, 55, 550, },
|
||||
[6] = { 30, 2800, 30, 300, },
|
||||
[7] = { 20, 2500, 15, 150, },
|
||||
[8] = { 10, 2300, 10, 100, },
|
||||
[9] = { 0, 0, 0, 50, }
|
||||
}"
|
||||
|
||||
## Fan options
|
||||
register "options.fan.fine_grained_control" = "1"
|
||||
register "options.fan.step_size" = "2"
|
||||
|
||||
device generic 0 alias dptf_policy on end
|
||||
end
|
||||
end
|
||||
device ref cnvi_wifi on
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref i2c0 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""RTL5682""
|
||||
register "name" = ""RT58""
|
||||
register "desc" = ""Headset Codec""
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
|
||||
# Set the jd_src to RT5668_JD1 for jack detection
|
||||
register "property_count" = "1"
|
||||
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
|
||||
register "property_list[0].name" = ""realtek,jd-src""
|
||||
register "property_list[0].integer" = "1"
|
||||
device i2c 1a on end
|
||||
end
|
||||
end #I2C0
|
||||
device ref i2c1 on end # GPU
|
||||
device ref i2c2 on end # External GPU
|
||||
device ref i2c3 on
|
||||
chip drivers/i2c/tpm
|
||||
register "hid" = ""GOOG0005""
|
||||
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
|
||||
device i2c 50 on end
|
||||
end
|
||||
end
|
||||
device ref i2c5 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""ELAN0000""
|
||||
register "desc" = ""ELAN Touchpad""
|
||||
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
|
||||
register "wake" = "GPE0_DW2_14"
|
||||
register "detect" = "1"
|
||||
device i2c 15 on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp3 on
|
||||
# Enable PCIE 3 using clk 4
|
||||
register "pch_pcie_rp[PCH_RP(3)]" = "{
|
||||
.clk_src = 4,
|
||||
.clk_req = 4,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip drivers/net
|
||||
register "customized_leds" = "0x05af"
|
||||
register "wake" = "GPE0_DW0_07"
|
||||
register "device_index" = "0"
|
||||
register "add_acpi_dma_property" = "true"
|
||||
device pci 00.0 on end
|
||||
end
|
||||
end #RTL8111H Ethernet NIC
|
||||
device ref pcie_rp4 off end
|
||||
device ref pcie_rp6 off end
|
||||
device ref pcie_rp7 off end
|
||||
device ref pcie_rp8 on
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
|
||||
register "srcclk_pin" = "3"
|
||||
device generic 0 on end
|
||||
end
|
||||
# Enable SD Card PCIE 8 using clk 3
|
||||
register "pch_pcie_rp[PCH_RP(8)]" = "{
|
||||
.clk_src = 3,
|
||||
.clk_req = 3,
|
||||
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end #PCIE8 SD card
|
||||
device ref pcie_rp9 on
|
||||
# Enable NVMe PCIE 9 using clk 1
|
||||
register "pch_pcie_rp[PCH_RP(9)]" = "{
|
||||
.clk_src = 1,
|
||||
.clk_req = 1,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end #PCIE9-12 SSD
|
||||
device ref hda on
|
||||
chip drivers/generic/max98357a
|
||||
register "hid" = ""MX98360A""
|
||||
register "sdmode_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
|
||||
register "sdmode_delay" = "5"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref pch_espi on
|
||||
chip ec/google/chromeec
|
||||
use conn0 as mux_conn[0]
|
||||
use conn1 as mux_conn[1]
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
end
|
||||
device ref pmc hidden
|
||||
chip drivers/intel/pmc_mux
|
||||
device generic 0 on
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port1 as usb2_port
|
||||
use tcss_usb3_port3 as usb3_port
|
||||
device generic 0 alias conn0 on end
|
||||
end
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port3 as usb2_port
|
||||
use tcss_usb3_port1 as usb3_port
|
||||
device generic 1 alias conn1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref tcss_xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref tcss_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C1 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref tcss_usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C0 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
|
||||
device ref tcss_usb3_port3 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref xhci_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C0 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref usb2_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C1 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
|
||||
device ref usb2_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Camera""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port6 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port 1""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 2))"
|
||||
device ref usb2_port8 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port 0""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
|
||||
device ref usb2_port9 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "reset_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
|
||||
device ref usb2_port10 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port 1""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
|
||||
device ref usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port 0""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 2))"
|
||||
device ref usb3_port2 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
|||
Loading…
Reference in New Issue