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soc/intel/common/block/acpi: Factor out common smbus.asl 

This patch moves smbus.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.

TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify SBUS device present inside
common smbus.asl is still there.
2) Verify no ACPI error seen while running 'dmesg` from console.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ib1ae48f7ece3e521501d92c40cd551287ea2f1ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik 2020-10-03 21:42:50 +05:30
parent 73968fd14b
commit 3b3bbd4fba
14 changed files with 7 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/soc/intel/cannonlake/acpi/smbus.asl
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@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
// Intel SMBus Controller 0:1f.4
Device (SBUS)
{
Name (_ADR, 0x001f0004)
}

2
src/soc/intel/cannonlake/acpi/southbridge.asl
View File

@ -32,7 +32,7 @@
#include "serialio.asl"
/* SMBus 0:1f.4 */
#include "smbus.asl"
#include <soc/intel/common/block/acpi/acpi/smbus.asl>
/* ISH 0:13.0 */
#include "ish.asl"

0
src/soc/intel/elkhartlake/acpi/smbus.asl → src/soc/intel/common/block/acpi/acpi/smbus.asl
View File

8
src/soc/intel/denverton_ns/acpi/smbus.asl
View File

@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
// Intel SMBus Controller 0:1f.4
Device (SBUS)
{
Name (_ADR, 0x001f0004)
}

2
src/soc/intel/denverton_ns/acpi/southcluster.asl
View File

@ -117,7 +117,7 @@ Device (P2SB)
#include "pmc.asl"
// SMBus 0:1f.4
#include "smbus.asl"
#include <soc/intel/common/block/acpi/acpi/smbus.asl>
// Northpeak 0:1f.7
#include "npk.asl"

2
src/soc/intel/elkhartlake/acpi/southbridge.asl
View File

@ -30,7 +30,7 @@
#include "serialio.asl"
/* SMBus 0:1f.4 */
#include "smbus.asl"
#include <soc/intel/common/block/acpi/acpi/smbus.asl>
/* USB XHCI 0:14.0 */
#include "xhci.asl"

8
src/soc/intel/icelake/acpi/smbus.asl
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@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
// Intel SMBus Controller 0:1f.4
Device (SBUS)
{
Name (_ADR, 0x001f0004)
}

2
src/soc/intel/icelake/acpi/southbridge.asl
View File

@ -30,7 +30,7 @@
#include "serialio.asl"
/* SMBus 0:1f.4 */
#include "smbus.asl"
#include <soc/intel/common/block/acpi/acpi/smbus.asl>
/* USB XHCI 0:14.0 */
#include "xhci.asl"

8
src/soc/intel/jasperlake/acpi/smbus.asl
View File

@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* Intel SMBus Controller 0:1f.4 */
Device (SBUS)
{
Name (_ADR, 0x001f0004)
}

2
src/soc/intel/jasperlake/acpi/southbridge.asl
View File

@ -33,7 +33,7 @@
#include "serialio.asl"
/* SMBus 0:1f.4 */
#include "smbus.asl"
#include <soc/intel/common/block/acpi/acpi/smbus.asl>
/* ISH 0:12.0 */
#include "ish.asl"

2
src/soc/intel/skylake/acpi/pch.asl
View File

@ -36,7 +36,7 @@
#include "serialio.asl"
/* SMBus 0:1f.3 */
#include "smbus.asl"
#include <soc/intel/common/block/acpi/acpi/smbus.asl>
/* Storage Controllers */
#include "scs.asl"

8
src/soc/intel/skylake/acpi/smbus.asl
View File

@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
// Intel SMBus Controller 0:1f.4
Device (SBUS)
{
Name (_ADR, 0x001f0004)
}

8
src/soc/intel/tigerlake/acpi/smbus.asl
View File

@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* Intel SMBus Controller 0:1f.4 */
Device (SBUS)
{
Name (_ADR, 0x001f0004)
}

2
src/soc/intel/tigerlake/acpi/southbridge.asl
View File

@ -30,7 +30,7 @@
#include "serialio.asl"
/* SMBus 0:1f.4 */
#include "smbus.asl"
#include <soc/intel/common/block/acpi/acpi/smbus.asl>
/* ISH 0:12.0 */
#include "ish.asl"