sc7180: Add display hardware pipe line initialization
Add sc7180 display hardware pipeline programming support and invoke the display initialization from soc_init. Changes in V1: - added display init required check. - added edid read function using i2c communication. - added sn65dsi86 bridge driver to init bridge. - moved display initialization to mainboard file. Changes in V2: - moved diplay init sequence to mainboard file - moved edid read function to bridge driver. - calculated timing paramters using edid parameters. - removed command mode config code. - moved bridge driver to drivers/ti. - seperated out bridge and soc code with mainboard file as interface. Changes in V3: - add GPIO selection at runtime based on boardid. - add vbif register struct overlay. Changes in V4: - update gpio config for lazor board. Change-Id: I7d5e3f1781c48759553243abeb3d694f76cd008e Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Vinod Polimera
Julius Werner
parent
c4e0b0a313
commit
3b4c45efa2
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@ -13,6 +13,11 @@
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#define GPIO_SD_CD_L GPIO(69)
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#define GPIO_AMP_ENABLE GPIO(23)
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/* Display specific GPIOS */
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#define GPIO_BACKLIGHT_ENABLE GPIO(12)
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#define GPIO_EDP_BRIDGE_ENABLE (CONFIG(TROGDOR_REV0) ? GPIO(14) : GPIO(104))
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#define GPIO_EN_PP3300_DX_EDP (CONFIG(TROGDOR_REV0) ? GPIO(106) : GPIO(30))
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void setup_chromeos_gpios(void);
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#endif /* _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ */
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@ -1,9 +1,21 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootmode.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/i2c_simple.h>
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#include <drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h>
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#include <soc/display/mipi_dsi.h>
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#include <soc/display/mdssreg.h>
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#include <soc/qupv3_config.h>
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#include <soc/qupv3_i2c.h>
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#include <soc/usb.h>
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#include "board.h"
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#define BRIDGE_BUS 0x2
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#define BRIDGE_CHIP 0x2d
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static struct usb_board_data usb0_board_data = {
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.pll_bias_control_2 = 0x22,
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.imp_ctrl1 = 0x08,
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@ -20,7 +32,6 @@ static void setup_usb(void)
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static void qi2s_configure_gpios(void)
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{
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gpio_configure(GPIO(49), GPIO49_FUNC_MI2S_1_SCK,
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GPIO_NO_PULL, GPIO_8MA, GPIO_OUTPUT);
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@ -34,7 +45,6 @@ static void qi2s_configure_gpios(void)
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static void load_qup_fw(void)
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{
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qupv3_se_fw_load_and_init(QUPV3_0_SE1, SE_PROTOCOL_SPI, MIXED); /* ESIM SPI */
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qupv3_se_fw_load_and_init(QUPV3_0_SE2, SE_PROTOCOL_I2C, MIXED); /* EDP Bridge I2C */
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qupv3_se_fw_load_and_init(QUPV3_0_SE3, SE_PROTOCOL_UART, FIFO); /* BT UART */
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qupv3_se_fw_load_and_init(QUPV3_0_SE4, SE_PROTOCOL_I2C, MIXED); /* Pen Detect I2C */
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qupv3_se_fw_load_and_init(QUPV3_0_SE5, SE_PROTOCOL_I2C, MIXED); /* SAR I2C */
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@ -51,11 +61,60 @@ static void load_qup_fw(void)
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qupv3_se_fw_load_and_init(QUPV3_1_SE5, SE_PROTOCOL_I2C, MIXED); /* Codec I2C */
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}
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static void configure_display(void)
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{
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printk(BIOS_INFO, "%s: Bridge gpio init\n", __func__);
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/* Bridge Enable GPIO */
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gpio_output(GPIO_EDP_BRIDGE_ENABLE, 1);
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/* PP3300 EDP power supply */
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gpio_output(GPIO_EN_PP3300_DX_EDP, 1);
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}
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static void display_init(struct edid *edid)
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{
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uint32_t dsi_bpp = 24;
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uint32_t lanes = 4;
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if (mdss_dsi_config(edid, lanes, dsi_bpp))
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return;
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sn65dsi86_bridge_configure(BRIDGE_BUS, BRIDGE_CHIP, edid, lanes, dsi_bpp);
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mdp_dsi_video_config(edid);
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mdss_dsi_video_mode_config(edid, dsi_bpp);
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mdp_dsi_video_on();
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}
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static void display_startup(void)
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{
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static struct edid ed;
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enum dp_pll_clk_src ref_clk = SN65_SEL_19MHZ;
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i2c_init(QUPV3_0_SE2, I2C_SPEED_FAST); /* EDP Bridge I2C */
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if (display_init_required()) {
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configure_display();
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mdelay(250); /* Delay for the panel to be up */
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sn65dsi86_bridge_init(BRIDGE_BUS, BRIDGE_CHIP, ref_clk);
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if (sn65dsi86_bridge_read_edid(BRIDGE_BUS, BRIDGE_CHIP, &ed) < 0)
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return;
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printk(BIOS_INFO, "display init!\n");
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/* Configure backlight */
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gpio_output(GPIO_BACKLIGHT_ENABLE, 1);
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display_init(&ed);
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set_vbe_mode_info_valid(&ed, (uintptr_t)0);
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} else
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printk(BIOS_INFO, "Skipping display init.\n");
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}
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static void mainboard_init(struct device *dev)
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{
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setup_usb();
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qi2s_configure_gpios();
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load_qup_fw();
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display_startup();
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}
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static void mainboard_enable(struct device *dev)
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@ -13,6 +13,10 @@ config SOC_QUALCOMM_SC7180
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select ARM64_USE_ARCH_TIMER
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select SOC_QUALCOMM_COMMON
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select HAVE_UART_SPECIAL
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select BOOTBLOCK_CONSOLE
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select MAINBOARD_FORCE_NATIVE_VGA_INIT
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select HAVE_LINEAR_FRAMEBUFFER
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if SOC_QUALCOMM_SC7180
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@ -62,6 +62,7 @@ ramstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy_pll.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/mdss.c
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################################################################################
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@ -0,0 +1,191 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/mmio.h>
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#include <console/console.h>
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#include <delay.h>
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#include <edid.h>
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#include <soc/display/mdssreg.h>
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#define MDSS_MDP_MAX_PREFILL_FETCH 25
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static void mdss_source_pipe_config(struct edid *edid)
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{
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uint32_t img_size, out_size, stride;
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uint32_t fb_off = 0;
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uint32_t flip_bits = 0;
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uint32_t src_xy = 0;
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uint32_t dst_xy = 0;
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/* write active region size*/
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img_size = (edid->mode.va << 16) | edid->mode.ha;
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out_size = img_size;
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stride = (edid->mode.ha * edid->framebuffer_bits_per_pixel/8);
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if (!fb_off) { /* left */
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dst_xy = (edid->mode.vborder << 16) | edid->mode.hborder;
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src_xy = dst_xy;
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} else { /* right */
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dst_xy = (edid->mode.vborder << 16);
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src_xy = (edid->mode.vborder << 16) | fb_off;
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}
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printk(BIOS_INFO, "%s: src=%x fb_off=%x src_xy=%x dst_xy=%x\n",
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__func__, out_size, fb_off, src_xy, dst_xy);
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write32(&mdp_sspp->sspp_src_ystride0, stride);
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write32(&mdp_sspp->sspp_src_size, out_size);
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write32(&mdp_sspp->sspp_out_size, out_size);
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write32(&mdp_sspp->sspp_src_xy, src_xy);
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write32(&mdp_sspp->sspp_out_xy, dst_xy);
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/* Tight Packing 4bpp Alpha 8-bit A R B G */
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write32(&mdp_sspp->sspp_src_format, 0x000236ff);
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write32(&mdp_sspp->sspp_src_unpack_pattern, 0x03020001);
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flip_bits |= BIT(31);
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write32(&mdp_sspp->sspp_sw_pic_ext_c0_req_pixels, out_size);
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write32(&mdp_sspp->sspp_sw_pic_ext_c1c2_req_pixels, out_size);
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write32(&mdp_sspp->sspp_sw_pic_ext_c3_req_pixels, out_size);
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write32(&mdp_sspp->sspp_src_op_mode, flip_bits);
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}
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static void mdss_vbif_setup(void)
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{
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write32(&vbif_rt->vbif_out_axi_amemtype_conf0, 0x33333333);
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write32(&vbif_rt->vbif_out_axi_amemtype_conf1, 0x00333333);
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}
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static void mdss_intf_tg_setup(struct edid *edid)
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{
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uint32_t hsync_period, vsync_period;
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uint32_t hsync_start_x, hsync_end_x;
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uint32_t display_hctl, hsync_ctl, display_vstart, display_vend;
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hsync_period = edid->mode.ha + edid->mode.hbl;
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vsync_period = edid->mode.va + edid->mode.vbl;
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hsync_start_x = edid->mode.hbl - edid->mode.hso;
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hsync_end_x = hsync_period - edid->mode.hso - 1;
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display_vstart = (edid->mode.vbl - edid->mode.vso) * hsync_period;
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display_vend = ((vsync_period - edid->mode.vso) * hsync_period) - 1;
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hsync_ctl = (hsync_period << 16) | edid->mode.hspw;
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display_hctl = (hsync_end_x << 16) | hsync_start_x;
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write32(&mdp_intf->intf_hsync_ctl, hsync_ctl);
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write32(&mdp_intf->intf_vysnc_period_f0,
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vsync_period * hsync_period);
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write32(&mdp_intf->intf_vysnc_pulse_width_f0,
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edid->mode.vspw * hsync_period);
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write32(&mdp_intf->intf_disp_hctl, display_hctl);
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write32(&mdp_intf->intf_disp_v_start_f0, display_vstart);
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write32(&mdp_intf->intf_disp_v_end_f0, display_vend);
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write32(&mdp_intf->intf_underflow_color, 0x00);
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write32(&mdp_intf->intf_panel_format, 0x2100);
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}
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static void mdss_intf_fetch_start_config(struct edid *edid)
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{
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uint32_t v_total, h_total, fetch_start, vfp_start;
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uint32_t prefetch_avail, prefetch_needed;
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uint32_t fetch_enable = BIT(31);
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/*
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* MDP programmable fetch is for MDP with rev >= 1.05.
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* Programmable fetch is not needed if vertical back porch
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* plus vertical puls width is >= 25.
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*/
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if ((edid->mode.vbl - edid->mode.vso) >= MDSS_MDP_MAX_PREFILL_FETCH)
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return;
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/*
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* Fetch should always be outside the active lines. If the fetching
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* is programmed within active region, hardware behavior is unknown.
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*/
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v_total = edid->mode.va + edid->mode.vbl;
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h_total = edid->mode.ha + edid->mode.hbl;
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vfp_start = edid->mode.va + edid->mode.vbl - edid->mode.vso;
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prefetch_avail = v_total - vfp_start;
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prefetch_needed = MDSS_MDP_MAX_PREFILL_FETCH - edid->mode.vbl + edid->mode.vso;
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/*
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* In some cases, vertical front porch is too high. In such cases limit
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* the mdp fetch lines as the last (25 - vbp - vpw) lines of
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* vertical front porch.
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*/
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if (prefetch_avail > prefetch_needed)
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prefetch_avail = prefetch_needed;
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fetch_start = (v_total - prefetch_avail) * h_total + h_total + 1;
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write32(&mdp_intf->intf_prof_fetch_start, fetch_start);
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write32(&mdp_intf->intf_config, fetch_enable);
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}
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static void mdss_layer_mixer_setup(struct edid *edid)
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{
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uint32_t mdp_rgb_size;
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uint32_t left_staging_level;
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/* write active region size*/
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mdp_rgb_size = (edid->mode.va << 16) | edid->mode.ha;
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write32(&mdp_layer_mixer->layer_out_size, mdp_rgb_size);
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write32(&mdp_layer_mixer->layer_op_mode, 0x0);
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for (int i = 0; i < 6; i++) {
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write32(&mdp_layer_mixer->layer_blend[i].layer_blend_op, 0x100);
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write32(&mdp_layer_mixer->layer_blend[i].layer_blend_const_alpha, 0x00ff0000);
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}
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/* Enable border fill */
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left_staging_level = BIT(24);
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left_staging_level |= BIT(1);
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/* Base layer for layer mixer 0 */
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write32(&mdp_ctl->ctl_layer0, left_staging_level);
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}
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static void mdss_vbif_qos_remapper_setup(void)
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{
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/*
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* VBIF remapper registers are used for translating internal display hardware
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* priority level (from 0 to 7) into system fabric priority level.
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* These remapper settings are defined for all the clients which corresponds
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* to the xin clients connected to SSPP on VBIF.
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*/
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write32(&vbif_rt->qos_rp_remap[0].vbif_xinl_qos_rp_remap, 0x00000003);
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write32(&vbif_rt->qos_rp_remap[1].vbif_xinl_qos_rp_remap, 0x11111113);
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write32(&vbif_rt->qos_rp_remap[2].vbif_xinl_qos_rp_remap, 0x22222224);
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write32(&vbif_rt->qos_rp_remap[3].vbif_xinl_qos_rp_remap, 0x33333334);
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write32(&vbif_rt->qos_rp_remap[4].vbif_xinl_qos_rp_remap, 0x44444445);
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write32(&vbif_rt->qos_rp_remap[7].vbif_xinl_qos_rp_remap, 0x77777776);
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write32(&vbif_rt->qos_lvl_remap[0].vbif_xinl_qos_lvl_remap, 0x00000003);
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write32(&vbif_rt->qos_lvl_remap[1].vbif_xinl_qos_lvl_remap, 0x11111113);
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write32(&vbif_rt->qos_lvl_remap[2].vbif_xinl_qos_lvl_remap, 0x22222224);
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write32(&vbif_rt->qos_lvl_remap[3].vbif_xinl_qos_lvl_remap, 0x33333334);
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write32(&vbif_rt->qos_lvl_remap[4].vbif_xinl_qos_lvl_remap, 0x44444445);
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write32(&vbif_rt->qos_lvl_remap[5].vbif_xinl_qos_lvl_remap, 0x77777776);
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}
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void mdp_dsi_video_config(struct edid *edid)
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{
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mdss_intf_tg_setup(edid);
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mdss_intf_fetch_start_config(edid);
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mdss_vbif_setup();
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mdss_vbif_qos_remapper_setup();
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mdss_source_pipe_config(edid);
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mdss_layer_mixer_setup(edid);
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/* Select Video Mode Interface */
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write32(&mdp_ctl->ctl_top, 0x0);
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/* PPB0 to INTF1 */
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write32(&mdp_ctl->ctl_intf_active, BIT(1));
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write32(&mdp_intf->intf_mux, 0x0F0000);
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}
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void mdp_dsi_video_on(void)
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{
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uint32_t ctl0_reg_val;
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ctl0_reg_val = VIG_0 | LAYER_MIXER_0 | CTL | INTF;
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write32(&mdp_ctl->ctl_intf_flush, 0x2);
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write32(&mdp_ctl->ctl_flush, ctl0_reg_val);
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}
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