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intel/haswell: Replace monotonic timer

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Remove implementation of 24 MHz clock, available only
on Haswell ULT SKUs. Use TSC_MONOTONIC_TIMER instead
for all boards.

Change-Id: Ic4aeb084d1b0913368f5eaa46e1bd68411435517
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Kyösti Mälkki 2019-07-06 09:51:58 +03:00 committed by Martin Roth
parent 8b9a3ec93a
commit 3b50c05bb2
5 changed files with 1 additions and 68 deletions
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1
src/cpu/intel/haswell/Kconfig
View file

@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS
select SSE2
select UDELAY_TSC
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select SUPPORT_CPU_UCODE_IN_CBFS
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE

8
src/cpu/intel/haswell/Makefile.inc
View file

@ -16,14 +16,6 @@ postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
smm-y += finalize.c
smm-y += tsc_freq.c
ifneq ($(CONFIG_TSC_MONOTONIC_TIMER),y)
bootblock-y += monotonic_timer.c
romstage-y += monotonic_timer.c
postcar-y += monotonic_timer.c
ramstage-y += monotonic_timer.c
smm-y += monotonic_timer.c
endif
bootblock-y += ../car/non-evict/cache_as_ram.S
bootblock-y += ../car/bootblock.c
bootblock-y += ../../x86/early_reset.S

58
src/cpu/intel/haswell/monotonic_timer.c
View file

@ -1,58 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <cpu/x86/msr.h>
#include <timer.h>
#define MSR_COUNTER_24_MHz 0x637
static struct monotonic_counter {
int initialized;
struct mono_time time;
uint32_t last_value;
} mono_counter;
static inline uint32_t read_counter_msr(void)
{
/* Even though the MSR is 64-bit it is assumed that the hardware
* is polled frequently enough to only use the lower 32-bits. */
msr_t counter_msr;
counter_msr = rdmsr(MSR_COUNTER_24_MHz);
return counter_msr.lo;
}
void timer_monotonic_get(struct mono_time *mt)
{
uint32_t current_tick;
uint32_t usecs_elapsed;
if (!mono_counter.initialized) {
mono_counter.last_value = read_counter_msr();
mono_counter.initialized = 1;
}
current_tick = read_counter_msr();
usecs_elapsed = (current_tick - mono_counter.last_value) / 24;
/* Update current time and tick values only if a full tick occurred. */
if (usecs_elapsed) {
mono_time_add_usecs(&mono_counter.time, usecs_elapsed);
mono_counter.last_value = current_tick;
}
/* Save result. */
*mt = mono_counter.time;
}

1
src/mainboard/asrock/h81m-hds/Kconfig
View file

@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS
select SOUTHBRIDGE_INTEL_LYNXPOINT
select SUPERIO_NUVOTON_NCT6776
select SUPERIO_NUVOTON_NCT6776_COM_A
select TSC_MONOTONIC_TIMER
config CBFS_SIZE
hex

1
src/mainboard/supermicro/x10slm-f/Kconfig
View file

@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS
select SOUTHBRIDGE_INTEL_LYNXPOINT
select SUPERIO_NUVOTON_NCT6776
select SUPERIO_NUVOTON_NCT6776_COM_A
select TSC_MONOTONIC_TIMER
config CBFS_SIZE
hex