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intel/broadwell: Implement proper backlight PWM config 

Port the backlight-PWM handling from Skylake instead of the previously
used Haswell version. We use a 200Hz PWM signal for all boards. Which
is higher than the previous devicetree value, 183Hz, but that was over-
ridden by the VBIOS anyway. 200Hz is still very low, considering LED
backlights, but accurate values are unknown at this time.

Lynx Point, the PCH for Haswell and Broadwell, is a transition point
for the backlight-PWM config. On platforms with a PCH, we have:

  o Before Lynx Point:
    The CPU has no PWM pin and sends the PWM duty-cycle setting
    to the PCH. The PCH can choose to ignore that and use its own
    setting (BLM_PCH_OVERRIDE_ENABLE).
    We use the CPU setting on these platforms.
  o Lynx Point + Haswell:
    The CPU has an additional PWM pin but can be set up to send
    its setting to the PCH as before. The PCH can still choose
    to ignore that.
    We use the CPU setting with Haswell.
  o Lynx Point + Broadwell:
    The CPU can't send its setting to the PCH anymore. BLM_PCH_
    OVERRIDE_ENABLE must always be set(!) if the PCH PWM pin is
    used (it virtually always is).
    We have to use the PCH setting in this case.
  o After Lynx Point:
    Same as with Broadwell, only BLM_PCH_OVERRIDE_ENABLE is
    implied and the bit not implemented anymore.

Change-Id: I1d61d9b3f1802ebe18799fc4d06f1f1d3b54c924
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Nico Huber 2019-10-08 20:24:05 +02:00 committed by Patrick Georgi
parent 9a4ca626d8
commit 3b57a7c37b
10 changed files with 49 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/mainboard/google/auron/variants/auron_paine/devicetree.cb
View File

@ -9,9 +9,8 @@ chip soc/intel/broadwell
# Enable HDMI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
# Set backlight PWM values for eDP
register "gpu_cpu_backlight" = "0x00000200"
register "gpu_pch_backlight" = "0x04000000"
# Set backlight PWM value for eDP
register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP

5
src/mainboard/google/auron/variants/auron_yuna/devicetree.cb
View File

@ -9,9 +9,8 @@ chip soc/intel/broadwell
# Enable HDMI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
# Set backlight PWM values for eDP
register "gpu_cpu_backlight" = "0x00000200"
register "gpu_pch_backlight" = "0x04000000"
# Set backlight PWM value for eDP
register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP

5
src/mainboard/google/auron/variants/buddy/devicetree.cb
View File

@ -9,9 +9,8 @@ chip soc/intel/broadwell
# Enable HDMI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
# Set backlight PWM values for eDP
register "gpu_cpu_backlight" = "0x00000200"
register "gpu_pch_backlight" = "0x04000000"
# Set backlight PWM value for eDP
register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP

5
src/mainboard/google/auron/variants/gandof/devicetree.cb
View File

@ -9,9 +9,8 @@ chip soc/intel/broadwell
# Enable HDMI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
# Set backlight PWM values for eDP
register "gpu_cpu_backlight" = "0x00000200"
register "gpu_pch_backlight" = "0x04000000"
# Set backlight PWM value for eDP
register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP

5
src/mainboard/google/auron/variants/lulu/devicetree.cb
View File

@ -9,9 +9,8 @@ chip soc/intel/broadwell
# Enable HDMI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
# Set backlight PWM values for eDP
register "gpu_cpu_backlight" = "0x00000200"
register "gpu_pch_backlight" = "0x04000000"
# Set backlight PWM value for eDP
register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP

5
src/mainboard/google/auron/variants/samus/devicetree.cb
View File

@ -9,9 +9,8 @@ chip soc/intel/broadwell
# Enable DDI2 Hotplug with 6ms pulse
register "gpu_dp_c_hotplug" = "0x06"
# Set backlight PWM values for eDP
register "gpu_cpu_backlight" = "0x00000200"
register "gpu_pch_backlight" = "0x04000200"
# Set backlight PWM value for eDP
register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP

5
src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb
View File

@ -6,9 +6,8 @@ chip soc/intel/broadwell
# Enable DDI1 Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
# Set backlight PWM values for eDP
register "gpu_cpu_backlight" = "0x00000200"
register "gpu_pch_backlight" = "0x04000200"
# Set backlight PWM value for eDP
register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP

5
src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb
View File

@ -6,9 +6,8 @@ chip soc/intel/broadwell
# Enable DDI1 Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
# Set backlight PWM values for eDP
register "gpu_cpu_backlight" = "0x00000200"
register "gpu_pch_backlight" = "0x04000200"
# Set backlight PWM value for eDP
register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP

7
src/soc/intel/broadwell/chip.h
View File

@ -117,8 +117,11 @@ struct soc_intel_broadwell_config {
u16 gpu_panel_power_backlight_off_delay;
/* Panel backlight settings */
u32 gpu_cpu_backlight;
u32 gpu_pch_backlight;
unsigned int gpu_pch_backlight_pwm_hz;
enum {
GPU_BACKLIGHT_POLARITY_HIGH = 0,
GPU_BACKLIGHT_POLARITY_LOW,
} gpu_pch_backlight_polarity;
/*
* Graphics CD Clock Frequency

34
src/soc/intel/broadwell/igd.c
View File

@ -335,14 +335,34 @@ static void igd_setup_panel(struct device *dev)
gtt_write(PCH_PP_DIVISOR, reg32);
}
/* Enable Backlight if needed */
if (conf->gpu_cpu_backlight) {
gtt_write(BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE);
gtt_write(BLC_PWM_CPU_CTL, conf->gpu_cpu_backlight);
/* So far all devices seem to use the PCH PWM function.
The CPU PWM registers are all zero after reset. */
if (conf->gpu_pch_backlight_pwm_hz) {
/* For Lynx Point-LP:
Reference clock is 24MHz. We can choose either a 16
or a 128 step increment. Use 16 if we would have less
than 100 steps otherwise. */
const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100;
unsigned int pwm_increment, pwm_period;
u32 south_chicken2;
south_chicken2 = gtt_read(SOUTH_CHICKEN2);
if (conf->gpu_pch_backlight_pwm_hz > hz_limit) {
pwm_increment = 16;
south_chicken2 &= ~(1 << 5);
} else {
pwm_increment = 128;
south_chicken2 |= 1 << 5;
}
if (conf->gpu_pch_backlight) {
gtt_write(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE);
gtt_write(BLC_PWM_PCH_CTL2, conf->gpu_pch_backlight);
gtt_write(SOUTH_CHICKEN2, south_chicken2);
pwm_period = 24 * 1000 * 1000 / pwm_increment / conf->gpu_pch_backlight_pwm_hz;
/* Start with a 50% duty cycle. */
gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2);
gtt_write(BLC_PWM_PCH_CTL1,
(conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 |
BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE);
}
}