diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c
index d5bffea8f0..5e22d6e7d6 100644
--- a/src/mainboard/google/veyron_pinky/bootblock.c
+++ b/src/mainboard/google/veyron_pinky/bootblock.c
@@ -1,6 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright 2014 Rockchip Inc.
  * Copyright 2014 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -17,8 +18,25 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+#include <arch/io.h>
 #include <bootblock_common.h>
+#include <soc/rockchip/rk3288/grf.h>
+#include <soc/rockchip/rk3288/spi.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 void bootblock_mainboard_init(void)
 {
+	/* i2c1 for tpm*/
+	writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
+
+	/* spi2 for firmware ROM */
+	writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
+	writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS);
+
+	/* spi0 for chrome ec */
+	writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
+	rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
+
+	setup_chromeos_gpios();
 }
diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c
index d7bc67a38d..eec3456613 100644
--- a/src/soc/rockchip/rk3288/bootblock.c
+++ b/src/soc/rockchip/rk3288/bootblock.c
@@ -17,34 +17,28 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#include <console/console.h>
-#include <arch/cache.h>
 #include <arch/io.h>
 #include <bootblock_common.h>
+#include <console/console.h>
+#include <soc/rockchip/rk3288/grf.h>
+#include "addressmap.h"
 #include "timer.h"
 #include "clock.h"
-#include "grf.h"
-#include "spi.h"
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <soc/rockchip/rk3288/i2c.h>
 
 static void bootblock_cpu_init(void)
 {
-	writel(IOMUX_UART2, &rk3288_grf->iomux_uart2);
-	writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
-	writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
-	/*i2c1 for tpm*/
-	writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
-
-	/* spi0 for chrome ec */
-	writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
 	rk3288_init_timer();
-	console_init();
-	rkclk_init();
 
-	/*i2c1 for tpm 400khz*/
-	i2c_init(1, 400000);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS);
-	rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
-	setup_chromeos_gpios();
+	if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_UART)) {
+		switch (CONFIG_CONSOLE_SERIAL_UART_ADDRESS) {
+		case UART2_BASE:
+			writel(IOMUX_UART2, &rk3288_grf->iomux_uart2);
+			break;
+		default:
+			die("TODO: Handle setup for console UART if needed");
+		}
+		console_init();
+	}
+
+	rkclk_init();
 }