cpu/intel/pineview: Include speedstep

Needed to generate cpu entries.

Change-Id: Ia3f5137c7642bb9f79562cc9d6e6881aca749179
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/cpu/intel/socket_FCBGA559/Makefile.inc

@@ -6,6 +6,7 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
+subdirs-y += ../speedstep
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
 romstage-y += ../car/romstage.c

src/northbridge/intel/pineview/northbridge.c

@@ -153,6 +153,7 @@ static struct device_operations pci_domain_ops = {
 	.init             = mch_domain_init,
 	.scan_bus         = pci_domain_scan_bus,
 	.ops_pci_bus	  = pci_bus_default_ops,
+	.acpi_fill_ssdt_generator = generate_cpu_entries,
 };
 
 static void cpu_bus_init(device_t dev)