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soc/intel/common: Use per-soc definition for BAR sizes

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The various platform BARs are not always the same size across different
SOCs, so use the defined size rather than a hardcoded value.

This results in the following change on TGL which increased the MCHBAR
size to 128K:

-system 00:00: [mem 0xfedc0000-0xfeddffff] has been reserved
+system 00:00: [mem 0xfedc0000-0xfedc7fff] has been reserved

And fixes the following error output from the kernel:

resource sanity check: requesting [mem 0xfedc0000-0xfedcdfff],
  which spans more than pnp 00:00 [mem 0xfedc0000-0xfedc7fff]

Change-Id: I82796c2fc81dec883f3c69ae7bdcedc7d3f16c64
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Duncan Laurie 2020-11-09 09:47:00 -08:00 committed by Duncan Laurie
parent 15ca9034b3
commit 3b70ad8ecf
1 changed files with 3 additions and 3 deletions
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6
src/soc/intel/common/block/acpi/acpi/northbridge.asl
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@ -253,17 +253,17 @@ Device (PDRC)
/* MCH BAR _BAS will be updated in _CRS below according to
* B0:D0:F0:Reg.48h
*/
Memory32Fixed (ReadWrite, 0, 0x08000, MCHB)
Memory32Fixed (ReadWrite, 0, MCH_BASE_SIZE, MCHB)
/* DMI BAR _BAS will be updated in _CRS below according to
* B0:D0:F0:Reg.68h
*/
Memory32Fixed (ReadWrite, 0, 0x01000, DMIB)
Memory32Fixed (ReadWrite, 0, DMI_BASE_SIZE, DMIB)
/* EP BAR _BAS will be updated in _CRS below according to
* B0:D0:F0:Reg.40h
*/
Memory32Fixed (ReadWrite, 0, 0x01000, EGPB)
Memory32Fixed (ReadWrite, 0, EP_BASE_SIZE, EGPB)
/* PCI Express BAR _BAS and _LEN will be updated in
* _CRS below according to B0:D0:F0:Reg.60h