mb/google/Screebo: Enable AUX DC biasing on C0

SKU1A C0 has no redriver, so enable SBU muxing in the SoC.

BUG=b:283044004
BRANCH=none
TEST=Voltages are correct on the C0 and C1 AUX bias pins

Change-Id: I18b4ade2c60c270855fb2e733a9201539e08d8ba
Signed-off-by: mike <mike5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>

src/mainboard/google/rex/variants/screebo/Makefile.inc

@@ -3,3 +3,4 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 romstage-y += memory.c
 ramstage-y += gpio.c
+ramstage-y += variant.c

src/mainboard/google/rex/variants/screebo/overridetree.cb

@@ -1,3 +1,11 @@
+fw_config
+	field MB_CONFIG 5 7
+		option MB_UNKNOWN		0
+		option MB_TYPEC			1
+		option MB_TBT			2
+	end
+end
+
 chip soc/intel/meteorlake
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC1)"	# USB2_C1

src/mainboard/google/rex/variants/screebo/variant.c

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <chip.h>
+#include <fw_config.h>
+#include <baseboard/variants.h>
+
+void variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config)
+{
+    /* SOC Aux orientation override:
+	* This is a bitfield that corresponds to up to 4 TCSS ports.
+	* Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
+	* TcssAuxOri = 0101b
+	* Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
+	* Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
+	* motherboard to USBC connector
+    */
+	if (fw_config_probe(FW_CONFIG(MB_CONFIG, MB_TYPEC))) {
+		config->typec_aux_bias_pads[1].pad_auxp_dc = GPP_C16;
+		config->typec_aux_bias_pads[1].pad_auxn_dc = GPP_C17;
+		config->tcss_aux_ori = 0x04;
+	}
+}