nb/intel/sandybridge: refactor lane_registers[]
Rename array and use defines for the values. The patch doesn't change the resulting binary when using BUILD_TIMELESS=1 Change-Id: I774373d231a0f4a2fe82ab7c6f1318fc56bcc678 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38405 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -1040,10 +1040,10 @@ void dram_mrscommands(ramctr_timing *ctrl)
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}
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}
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static const u32 lane_registers[] = {
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0x0000, 0x0200, 0x0400, 0x0600,
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0x1000, 0x1200, 0x1400, 0x1600,
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0x0800
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static const u32 lane_base[] = {
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LANEBASE_B0, LANEBASE_B1, LANEBASE_B2, LANEBASE_B3,
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LANEBASE_B4, LANEBASE_B5, LANEBASE_B6, LANEBASE_B7,
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LANEBASE_ECC
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};
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void program_timings(ramctr_timing *ctrl, int channel)
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@ -1155,9 +1155,7 @@ void program_timings(ramctr_timing *ctrl, int channel)
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shift_402x) << (8 * slotrank);
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FOR_ALL_LANES {
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MCHBAR32(lane_registers[lane] + 0x10 + channel * 0x100 +
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4 * slotrank)
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=
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MCHBAR32(lane_base[lane] + 0x10 + channel * 0x100 + 4 * slotrank) =
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(((ctrl->timings[channel][slotrank].lanes[lane].
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timA + shift) & 0x3f)
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@ -1170,9 +1168,7 @@ void program_timings(ramctr_timing *ctrl, int channel)
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| ((ctrl->timings[channel][slotrank].lanes[lane].
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falling + shift) << 20));
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MCHBAR32(lane_registers[lane] + 0x20 + channel * 0x100 +
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4 * slotrank)
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=
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MCHBAR32(lane_base[lane] + 0x20 + channel * 0x100 + 4 * slotrank) =
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(((ctrl->timings[channel][slotrank].lanes[lane].
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timC + shift) & 0x3f)
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@ -1232,7 +1228,7 @@ static int does_lane_work(ramctr_timing *ctrl, int channel, int slotrank,
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int lane)
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{
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u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA;
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return ((MCHBAR32(lane_registers[lane] + channel * 0x100 + 4 +
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return ((MCHBAR32(lane_base[lane] + channel * 0x100 + 4 +
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((timA / 32) & 1) * 4) >> (timA % 32)) & 1);
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}
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@ -1894,7 +1890,7 @@ static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank)
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FOR_ALL_LANES {
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statistics[lane][timB] =
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!((MCHBAR32(lane_registers[lane] +
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!((MCHBAR32(lane_base[lane] +
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channel * 0x100 + 4 + ((timB / 32) & 1) * 4)
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>> (timB % 32)) & 1);
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}
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@ -2017,9 +2013,8 @@ static void adjust_high_timB(ramctr_timing *ctrl)
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wait_for_iosav(channel);
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FOR_ALL_LANES {
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u64 res = MCHBAR32(lane_registers[lane] + channel * 0x100 + 4);
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res |= ((u64) MCHBAR32(lane_registers[lane] +
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channel * 0x100 + 8)) << 32;
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u64 res = MCHBAR32(lane_base[lane] + channel * 0x100 + 4);
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res |= ((u64) MCHBAR32(lane_base[lane] + channel * 0x100 + 8)) << 32;
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old = ctrl->timings[channel][slotrank].lanes[lane].timB;
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ctrl->timings[channel][slotrank].lanes[lane].timB +=
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get_timB_high_adjust(res) * 64;
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@ -3025,9 +3020,9 @@ void write_controller_mr(ramctr_timing *ctrl)
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int channel, slotrank;
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FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
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MCHBAR32(0x0004 + channel * 0x100 + lane_registers[slotrank]) =
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MCHBAR32(0x0004 + channel * 0x100 + lane_base[slotrank]) =
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make_mr0(ctrl, slotrank);
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MCHBAR32(0x0008 + channel * 0x100 + lane_registers[slotrank]) =
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MCHBAR32(0x0008 + channel * 0x100 + lane_base[slotrank]) =
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make_mr1(ctrl, slotrank, channel);
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}
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}
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@ -133,6 +133,17 @@ enum platform_type {
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#define Cx(r, x) ((r) + ((x) * 0x400))
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#define CxLy(r, x, y) ((r) + ((x) * 0x400) + ((y) * 4))
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/* byte lane training register base addresses */
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#define LANEBASE_B0 0x0000
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#define LANEBASE_B1 0x0200
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#define LANEBASE_B2 0x0400
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#define LANEBASE_B3 0x0600
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#define LANEBASE_B4 0x1000
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#define LANEBASE_B5 0x1200
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#define LANEBASE_B6 0x1400
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#define LANEBASE_B7 0x1600
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#define LANEBASE_ECC 0x0800 /* ECC lane is in the middle of the data lanes */
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/* Register definitions */
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#define GDCRCLKRANKSUSED_ch(ch) Gz(0x0c00, ch) /* Indicates which rank is populated */
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#define GDCRCLKCOMP_ch(ch) Gz(0x0c04, ch) /* RCOMP result register */
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