soc/intel/common/lpss: Add lpss_is_controller_in_reset
Add new API function lpss_is_controller_in_reset that returns whether the LPSS controller is in reset. Also, add lpss.c to smm stage so that lpss_is_controller_in_reset can be used in smihandler. BUG=b:64030366 Change-Id: I0fe5c2890ee799b08482e487296a483fa8d42461 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -27,4 +27,7 @@ void lpss_reset_release(uintptr_t base);
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*/
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void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val);
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/* Check if controller is in reset. */
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bool lpss_is_controller_in_reset(uintptr_t base);
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#endif /* SOC_INTEL_COMMON_BLOCK_LPSS_H */
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@ -2,3 +2,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
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romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
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verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
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smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
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@ -39,6 +39,17 @@
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/* DMA Software Reset Control */
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#define LPSS_DMA_RST_RELEASE (1 << 2)
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bool lpss_is_controller_in_reset(uintptr_t base)
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{
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uint8_t *addr = (void *)base;
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uint32_t val = read32(addr + LPSS_RESET_CTL_REG);
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if (val == 0xFFFFFFFF)
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return true;
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return !(val & LPSS_CNT_RST_RELEASE);
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}
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void lpss_reset_release(uintptr_t base)
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{
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uint8_t *addr = (void *)base;
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