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soc/intel/skylake: remove PrimaryDisplay check 

Checking the PrimaryDisplay parameter (added by patch with Change
Id Ie3f9362676105e41c69139a094dbb9e8b865689f) isn`t required. The
display connected to PEG works  even if IGD is primary for output
image and at the same time this device is disabled

Tested on Asrock H110M-DVS with NVIDIA GTX 1060 GPU
Payload: tianocore edk2-stable201811-216-g51be9d0

Change-Id: I5615597881a151bb004676d914fbf40874ac1f68
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32615
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maxim Polyakov 2019-05-06 12:07:24 +03:00 committed by Patrick Georgi
parent d7d0b04d3a
commit 3ba380797b
1 changed files with 1 additions and 5 deletions
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6
src/soc/intel/skylake/romstage/romstage_fsp20.c
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@ -304,10 +304,6 @@ static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg,
*/
m_cfg->InternalGfx = 0;
m_cfg->IgdDvmt50PreAlloc = 0;
if (config->PrimaryDisplay == Display_iGFX)
m_cfg->PrimaryDisplay = Display_Auto;
else
m_cfg->PrimaryDisplay = config->PrimaryDisplay;
} else {
m_cfg->InternalGfx = 1;
/*
@ -319,8 +315,8 @@ static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg,
* a high resolution panel
*/
m_cfg->IgdDvmt50PreAlloc = 2;
m_cfg->PrimaryDisplay = config->PrimaryDisplay;
}
m_cfg->PrimaryDisplay = config->PrimaryDisplay;
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)