From 3bc41cf7b4a3c5aab69e8c4fd796720cde38a324 Mon Sep 17 00:00:00 2001 From: Alex Levin Date: Fri, 6 Mar 2020 10:54:10 -0800 Subject: [PATCH] mb/google/volteer: Enable FPMCU on volteer BUG=b:147500717 TEST=none Change-Id: I32fa27b399127dbf8608e0556c77431d2dad652d Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/39358 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../google/volteer/variants/baseboard/devicetree.cb | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 70b6186494..070e4f6786 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -153,7 +153,7 @@ chip soc/intel/tigerlake #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | - #| GSPI1 | Fingerprint MCU + #| GSPI1 | Fingerprint MCU | #| I2C0 | Audio | #| I2C1 | Touchscreen | #| I2C2 | WLAN, SAR0 | @@ -329,7 +329,16 @@ chip soc/intel/tigerlake device spi 0 on end end end # GSPI0 0xA0AA - device pci 1e.3 on end # GSPI1 0xA0AB + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)" + device spi 0 on end + end # FPMCU + end # GSPI1 0xA0AB device pci 1f.0 on end # eSPI 0xA080 - A09F device pci 1f.1 off end # P2SB 0xA0A0