/mb/google/hatch: Create jinlon variant
Create new variant for jinlon BUG=b:144150654 TEST=emerge-hatch coreboot chromeos-bootimage and boot on jinlon proto board Change-Id: I8deb29041475e38cbbf2f54519940f62b9f21822 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36681 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wisley Chen
Patrick Georgi
parent
f2cae5085c
commit
3bc70228a2
8 changed files with 367 additions and 0 deletions
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@ -92,6 +92,7 @@ config MAINBOARD_PART_NUMBER
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default "Hatch" if BOARD_GOOGLE_HATCH
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default "Hatch" if BOARD_GOOGLE_HATCH
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default "Helios" if BOARD_GOOGLE_HELIOS
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default "Helios" if BOARD_GOOGLE_HELIOS
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default "Helios_Diskswap" if BOARD_GOOGLE_HELIOS_DISKSWAP
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default "Helios_Diskswap" if BOARD_GOOGLE_HELIOS_DISKSWAP
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default "Jinlon" if BOARD_GOOGLE_JINLON
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default "Kindred" if BOARD_GOOGLE_KINDRED
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default "Kindred" if BOARD_GOOGLE_KINDRED
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default "Kohaku" if BOARD_GOOGLE_KOHAKU
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default "Kohaku" if BOARD_GOOGLE_KOHAKU
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default "Puff" if BOARD_GOOGLE_PUFF
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default "Puff" if BOARD_GOOGLE_PUFF
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@ -120,6 +121,7 @@ config VARIANT_DIR
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default "hatch" if BOARD_GOOGLE_HATCH
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default "hatch" if BOARD_GOOGLE_HATCH
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default "helios" if BOARD_GOOGLE_HELIOS
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default "helios" if BOARD_GOOGLE_HELIOS
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default "helios" if BOARD_GOOGLE_HELIOS_DISKSWAP
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default "helios" if BOARD_GOOGLE_HELIOS_DISKSWAP
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default "jinlon" if BOARD_GOOGLE_JINLON
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default "kindred" if BOARD_GOOGLE_KINDRED
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default "kindred" if BOARD_GOOGLE_KINDRED
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default "kohaku" if BOARD_GOOGLE_KOHAKU
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default "kohaku" if BOARD_GOOGLE_KOHAKU
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default "puff" if BOARD_GOOGLE_PUFF
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default "puff" if BOARD_GOOGLE_PUFF
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@ -15,6 +15,11 @@ config BOARD_GOOGLE_HATCH
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select BOARD_GOOGLE_BASEBOARD_HATCH
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select BOARD_GOOGLE_BASEBOARD_HATCH
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select BOARD_ROMSIZE_KB_32768
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select BOARD_ROMSIZE_KB_32768
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config BOARD_GOOGLE_JINLON
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bool "-> Jinlon"
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select BOARD_GOOGLE_BASEBOARD_HATCH
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select BOARD_ROMSIZE_KB_16384
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config BOARD_GOOGLE_KOHAKU
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config BOARD_GOOGLE_KOHAKU
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bool "-> Kohaku"
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bool "-> Kohaku"
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select BOARD_GOOGLE_BASEBOARD_HATCH
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select BOARD_GOOGLE_BASEBOARD_HATCH
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27
src/mainboard/google/hatch/variants/jinlon/Makefile.inc
Normal file
27
src/mainboard/google/hatch/variants/jinlon/Makefile.inc
Normal file
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@ -0,0 +1,27 @@
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## This file is part of the coreboot project.
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##
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## Copyright 2019 Google LLC
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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SPD_SOURCES = 4G_2400 # 0b000
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SPD_SOURCES += empty_ddr4 # 0b001
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SPD_SOURCES += 8G_2400 # 0b010
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SPD_SOURCES += 8G_2666 # 0b011
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SPD_SOURCES += 16G_2400 # 0b100
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SPD_SOURCES += 16G_2666 # 0b101
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SPD_SOURCES += 8G_3200 # 0b110
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SPD_SOURCES += 16G_3200 # 0b111
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SPD_SOURCES += 16G_2666_2bg # 0b1000
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SPD_SOURCES += 16G_3200_4bg # 0b1001
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bootblock-y += gpio.c
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ramstage-y += gpio.c
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110
src/mainboard/google/hatch/variants/jinlon/gpio.c
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110
src/mainboard/google/hatch/variants/jinlon/gpio.c
Normal file
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@ -0,0 +1,110 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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static const struct pad_config gpio_table[] = {
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/* A0 : NC */
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PAD_NC(GPP_A0, NONE),
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/* A6 : NC */
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PAD_NC(GPP_A6, NONE),
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/* A8 : NC */
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PAD_NC(GPP_A8, NONE),
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/* A10 : NC */
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PAD_NC(GPP_A10, NONE),
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/* C12 : FPMCU_PCH_BOOT1 */
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PAD_CFG_GPO(GPP_C12, 0, DEEP),
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/* F1 : NC */
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PAD_NC(GPP_F1, NONE),
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/* F3 : MEM_STRAP_3 */
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PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
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/* F10 : MEM_STRAP_2 */
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PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
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/* F11 : EMMC_CMD ==> NC */
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PAD_NC(GPP_F11, NONE),
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/* F12 : EMMC_DATA0 ==> NC */
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PAD_NC(GPP_F12, NONE),
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/* F13 : EMMC_DATA1 ==> NC */
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PAD_NC(GPP_F13, NONE),
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/* F14 : EMMC_DATA2 ==> NC */
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PAD_NC(GPP_F14, NONE),
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/* F15 : EMMC_DATA3 ==> NC */
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PAD_NC(GPP_F15, NONE),
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/* F16 : EMMC_DATA4 ==> NC */
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PAD_NC(GPP_F16, NONE),
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/* F17 : EMMC_DATA5 ==> NC */
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PAD_NC(GPP_F17, NONE),
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/* F18 : EMMC_DATA6 ==> NC */
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PAD_NC(GPP_F18, NONE),
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/* F19 : EMMC_DATA7 ==> NC */
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PAD_NC(GPP_F19, NONE),
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/* F20 : EMMC_RCLK ==> NC */
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PAD_NC(GPP_F20, NONE),
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/* F21 : EMMC_CLK ==> NC */
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PAD_NC(GPP_F21, NONE),
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/* F22 : EMMC_RESET# ==> NC */
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PAD_NC(GPP_F22, NONE),
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/* H19 : MEM_STRAP_0 */
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PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
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/* H22 : MEM_STRAP_1 */
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PAD_CFG_GPI(GPP_H22, NONE, PLTRST),
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};
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const struct pad_config *override_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(gpio_table);
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return gpio_table;
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}
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/*
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* GPIOs configured before ramstage
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* Note: the Hatch platform's romstage will configure
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* the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins
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* as inputs before it reads them, so they are not
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* needed in this table.
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*/
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static const struct pad_config early_gpio_table[] = {
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/* B15 : H1_SLAVE_SPI_CS_L */
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PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
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/* B16 : H1_SLAVE_SPI_CLK */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
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/* B17 : H1_SLAVE_SPI_MISO_R */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* C14 : BT_DISABLE_L */
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PAD_CFG_GPO(GPP_C14, 0, DEEP),
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/* PCH_WP_OD */
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PAD_CFG_GPI(GPP_C20, NONE, DEEP),
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/* C21 : H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
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/* C23 : WLAN_PE_RST# */
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PAD_CFG_GPO(GPP_C23, 1, DEEP),
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/* E1 : M2_SSD_PEDET */
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PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
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/* E5 : SATA_DEVSLP1 */
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PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
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/* F2 : MEM_CH_SEL */
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PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
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};
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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@ -0,0 +1,16 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/acpi/dptf.asl>
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef VARIANT_EC_H
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#define VARIANT_EC_H
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#include <baseboard/ec.h>
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#endif
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@ -0,0 +1,27 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#ifndef VARIANT_GPIO_H
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#define VARIANT_GPIO_H
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#include <baseboard/gpio.h>
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/* Memory configuration board straps */
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#define GPIO_MEM_CONFIG_0 GPP_H19
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#define GPIO_MEM_CONFIG_1 GPP_H22
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#define GPIO_MEM_CONFIG_2 GPP_F10
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#define GPIO_MEM_CONFIG_3 GPP_F3
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#endif
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159
src/mainboard/google/hatch/variants/jinlon/overridetree.cb
Normal file
159
src/mainboard/google/hatch/variants/jinlon/overridetree.cb
Normal file
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@ -0,0 +1,159 @@
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chip soc/intel/cannonlake
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoPci,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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[PchSerialIoIndexSPI0] = PchSerialIoPci,
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[PchSerialIoIndexSPI1] = PchSerialIoPci,
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[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
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[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| GSPI0 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| | before memory is up |
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#| GSPI1 | FP MCU |
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#| I2C0 | Touchpad |
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#| I2C1 | Touch screen |
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#| I2C4 | Audio |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.gspi[0] = {
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.speed_mhz = 1,
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.early_init = 1,
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},
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[4] = {
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.speed = I2C_SPEED_FAST,
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},
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}"
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# GPIO for SD card detect
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register "sdcard_cd_gpio" = "vSD3_CD_B"
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# Enable eMMC HS400
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register "ScsEmmcHs400Enabled" = "1"
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device domain 0 on
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device pci 15.0 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)"
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register "wake" = "GPE0_DW0_21"
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register "probed" = "1"
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device i2c 15 on end
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end
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end # I2C #0
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device pci 15.1 on
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chip drivers/i2c/hid
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register "generic.hid" = ""GTCH7503""
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register "generic.desc" = ""G2TOUCH Touchscreen""
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register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
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register "generic.probed" = "1"
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register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
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register "generic.reset_delay_ms" = "50"
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register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"
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register "generic.enable_delay_ms" = "1"
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register "generic.has_power_resource" = "1"
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register "generic.disable_gpio_export_in_crs" = "1"
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register "hid_desc_reg_offset" = "0x01"
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device i2c 40 on end
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end
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chip drivers/i2c/generic
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register "hid" = ""ELAN0001""
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register "desc" = ""ELAN Touchscreen""
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||||||
|
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
|
||||||
|
register "probed" = "1"
|
||||||
|
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
|
||||||
|
register "reset_delay_ms" = "100"
|
||||||
|
register "reset_off_delay_ms" = "5"
|
||||||
|
register "has_power_resource" = "1"
|
||||||
|
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"
|
||||||
|
register "enable_delay_ms" = "10"
|
||||||
|
register "enable_off_delay_ms" = "1"
|
||||||
|
device i2c 10 on end
|
||||||
|
end
|
||||||
|
chip drivers/i2c/hid
|
||||||
|
register "generic.hid" = ""GDIX0000""
|
||||||
|
register "generic.desc" = ""Goodix Touchscreen""
|
||||||
|
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
|
||||||
|
register "generic.probed" = "1"
|
||||||
|
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
|
||||||
|
register "generic.reset_delay_ms" = "120"
|
||||||
|
register "generic.reset_off_delay_ms" = "3"
|
||||||
|
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"
|
||||||
|
register "generic.enable_delay_ms" = "10"
|
||||||
|
register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
|
||||||
|
register "generic.stop_off_delay_ms" = "20"
|
||||||
|
register "generic.has_power_resource" = "1"
|
||||||
|
register "hid_desc_reg_offset" = "0x01"
|
||||||
|
device i2c 5d on end
|
||||||
|
end
|
||||||
|
chip drivers/i2c/hid
|
||||||
|
register "generic.hid" = ""ELAN2513""
|
||||||
|
register "generic.desc" = ""ELAN Touchscreen""
|
||||||
|
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
|
||||||
|
register "generic.probed" = "1"
|
||||||
|
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
|
||||||
|
register "generic.reset_delay_ms" = "20"
|
||||||
|
register "generic.reset_off_delay_ms" = "2"
|
||||||
|
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"
|
||||||
|
register "generic.enable_delay_ms" = "10"
|
||||||
|
register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
|
||||||
|
register "generic.stop_delay_ms" = "130"
|
||||||
|
register "generic.has_power_resource" = "1"
|
||||||
|
register "hid_desc_reg_offset" = "0x01"
|
||||||
|
device i2c 15 on end
|
||||||
|
end
|
||||||
|
end # I2C #1
|
||||||
|
device pci 15.2 off end # I2C #2
|
||||||
|
device pci 15.3 off end # I2C #3
|
||||||
|
device pci 19.0 on
|
||||||
|
chip drivers/i2c/generic
|
||||||
|
register "hid" = ""10EC5682""
|
||||||
|
register "name" = ""RT58""
|
||||||
|
register "desc" = ""Realtek RT5682""
|
||||||
|
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
|
||||||
|
register "property_count" = "1"
|
||||||
|
# Set the jd_src to RT5668_JD1 for jack detection
|
||||||
|
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
|
||||||
|
register "property_list[0].name" = ""realtek,jd-src""
|
||||||
|
register "property_list[0].integer" = "1"
|
||||||
|
device i2c 1a on end
|
||||||
|
end
|
||||||
|
end #I2C #4
|
||||||
|
device pci 1a.0 on end # eMMC
|
||||||
|
device pci 1e.3 on
|
||||||
|
chip drivers/spi/acpi
|
||||||
|
register "name" = ""CRFP""
|
||||||
|
register "hid" = "ACPI_DT_NAMESPACE_HID"
|
||||||
|
register "uid" = "1"
|
||||||
|
register "compat_string" = ""google,cros-ec-spi""
|
||||||
|
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)"
|
||||||
|
register "wake" = "GPE0_DW0_23"
|
||||||
|
device spi 1 on end
|
||||||
|
end # FPMCU
|
||||||
|
end # GSPI #1
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
Loading…
Reference in a new issue