nb/i945: Drop CHANNEL_XOR_RANDOMIZATION selection

CHANNEL_XOR_RANDOMIZATION is configurable for no reason.

Change-Id: I31e6ed6cb040dcba756cbfd2247d90753d372915
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Elyes HAOUAS 2019-05-22 16:57:54 +02:00 committed by Nico Huber
parent 30645bff5e
commit 3bf4e28fb8
13 changed files with 0 additions and 19 deletions

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@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_CMOS_DEFAULT
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_2048
select CHANNEL_XOR_RANDOMIZATION
select INTEL_INT15
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME

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@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_512
select CHANNEL_XOR_RANDOMIZATION
select MAINBOARD_HAS_NATIVE_VGA_INIT
select INTEL_GMA_HAVE_VBT

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@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_RESUME
select UDELAY_LAPIC
select BOARD_ROMSIZE_KB_1024
select CHANNEL_XOR_RANDOMIZATION
select INTEL_INT15
select I945_LVDS

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@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_512
select CHANNEL_XOR_RANDOMIZATION
select MAINBOARD_HAS_NATIVE_VGA_INIT
select REALTEK_8168_RESET if BOARD_GIGABYTE_GA_945GCM_S2L
select INTEL_GMA_HAVE_VBT

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@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_512
select CHANNEL_XOR_RANDOMIZATION
select INTEL_INT15
config MAINBOARD_DIR

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@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_512
select CHANNEL_XOR_RANDOMIZATION
select MAINBOARD_HAS_NATIVE_VGA_INIT
select INTEL_GMA_HAVE_VBT

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@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_1024
select CHANNEL_XOR_RANDOMIZATION
select INTEL_INT15
select OVERRIDE_CLOCK_DISABLE

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@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS
select INTEL_INT15
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_2048
select CHANNEL_XOR_RANDOMIZATION
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select H8_DOCK_EARLY_INIT

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@ -19,7 +19,6 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_2048
select CHANNEL_XOR_RANDOMIZATION
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select USE_OPTION_TABLE

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@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS
select INTEL_INT15
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_2048
select CHANNEL_XOR_RANDOMIZATION
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select H8_DOCK_EARLY_INIT

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@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_1024
select CHANNEL_XOR_RANDOMIZATION
select INTEL_INT15
config MAINBOARD_DIR

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@ -56,10 +56,6 @@ config I945_LVDS
for the LVDS port. A linear framebuffer is only supported for
LVDS.
config CHANNEL_XOR_RANDOMIZATION
bool
default n
config MMCONF_BASE_ADDRESS
hex
default 0xf0000000

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@ -2112,12 +2112,8 @@ static void sdram_post_jedec_initialization(struct sys_info *sysinfo)
if (sysinfo->interleaved) {
reg32 = MCHBAR32(DCC);
#if CONFIG(CHANNEL_XOR_RANDOMIZATION)
reg32 &= ~(1 << 10);
reg32 |= (1 << 9);
#else
reg32 &= ~(1 << 9);
#endif
MCHBAR32(DCC) = reg32;
}