intel/skylake: Add support to enable wake-on-usb attach/detach
Three things are required to enable wake-on-usb: 1. 5V to USB ports should be enabled in S3. 2. ASL file needs to have appropriate wake bit set. 3. XHCI controller should have the wake on attach/detach bit set for the corresponding port in PORTSCN register. Only part missing was #3. This CL adds support to allow mainboard to define a bitmap in devicetree corresponding to the ports that it wants to enable wake-on-usb feature. Based on the bitmap, wake on attach/detach bits in PORTSCN would be set by xhci.asl for the appropriate ports. BUG=chrome-os-partner:58734 BRANCH=None TEST=Verified that with port 5 enabled, chell wakes up from S3 on usb attach/detach. Change-Id: I40a22a450e52f74a0ab93ebb8170555d834ebdaf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17056 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -198,6 +198,10 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
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/* Fill in the Wifi Region id */
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/* Fill in the Wifi Region id */
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gnvs->cid1 = wifi_regulatory_domain();
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gnvs->cid1 = wifi_regulatory_domain();
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/* Set USB2/USB3 wake enable bitmaps. */
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gnvs->u2we = config->usb2_wake_enable_bitmap;
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gnvs->u3we = config->usb3_wake_enable_bitmap;
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}
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}
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unsigned long acpi_fill_mcfg(unsigned long current)
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unsigned long acpi_fill_mcfg(unsigned long current)
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@ -64,6 +64,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
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NHLA, 64, // 0x31 - NHLT Address
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NHLA, 64, // 0x31 - NHLT Address
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NHLL, 32, // 0x39 - NHLT Length
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NHLL, 32, // 0x39 - NHLT Length
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CID1, 16, // 0x3d - Wifi Country Identifier
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CID1, 16, // 0x3d - Wifi Country Identifier
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U2WE, 16, // 0x3f - USB2 Wake Enable Bitmap
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U3WE, 8, // 0x41 - USB3 Wake Enable Bitmap
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/* ChromeOS specific */
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/* ChromeOS specific */
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Offset (0x100),
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Offset (0x100),
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@ -15,6 +15,55 @@
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* GNU General Public License for more details.
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* GNU General Public License for more details.
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*/
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*/
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/*
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* USB Port Wake Enable (UPWE) on usb attach/detach
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* Arg0 - Port Number
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* Arg1 - Port 1 Status and control offset
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* Arg2 - xHCI Memory-mapped address
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*/
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Method (UPWE, 3, Serialized)
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{
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/* Local0 = Arg1 + ((Arg0 - 1) * 0x10) */
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Add (Arg1, Multiply (Subtract (Arg0, 1), 0x10), Local0)
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/* Map ((XMEM << 16) + Local0 in PSCR */
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OperationRegion (PSCR, SystemMemory,
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Add (ShiftLeft (Arg2, 16), Local0), 0x10)
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Field (PSCR, AnyAcc, NoLock, Preserve)
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{
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, 25,
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UPCE, 1,
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UPDE, 1,
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}
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Store (One, UPCE)
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Store (One, UPDE)
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}
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/*
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* USB Wake Enable Setup (UWES)
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* Arg0 - Port enable bitmap
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* Arg1 - Port 1 Status and control offset
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* Arg2 - xHCI Memory-mapped address
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*/
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Method (UWES, 3, Serialized)
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{
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Store (Arg0, Local0)
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While (One) {
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FindSetRightBit (Local0, Local1)
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If (LEqual (Local1, Zero)) {
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Break
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}
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UPWE (Local1, Arg1, Arg2)
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/*
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* Clear the lowest set bit in Local0 since it was
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* processed.
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* Local0 = Local0 & (Local0 - 1)
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*/
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And (Local0, Subtract (Local0, 1), Local0)
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}
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}
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/* XHCI Controller 0:14.0 */
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/* XHCI Controller 0:14.0 */
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Device (XHCI)
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Device (XHCI)
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@ -26,6 +75,8 @@ Device (XHCI)
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Method (_DSW, 3)
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Method (_DSW, 3)
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{
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{
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Store (Arg0, PMEE)
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Store (Arg0, PMEE)
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UWES (And (\U2WE, 0x3FF), 0x480, XMEM)
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UWES (And (\U3WE, 0x3F), 0x540, XMEM)
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}
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}
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Name (_S3D, 3) /* D3 supported in S3 */
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Name (_S3D, 3) /* D3 supported in S3 */
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@ -395,6 +395,12 @@ struct soc_intel_skylake_config {
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/* Use custom SD card detect GPIO configuration */
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/* Use custom SD card detect GPIO configuration */
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struct acpi_gpio sdcard_cd_gpio;
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struct acpi_gpio sdcard_cd_gpio;
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/* Wake Enable Bitmap for USB2 ports */
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u16 usb2_wake_enable_bitmap;
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/* Wake Enable Bitmap for USB3 ports */
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u8 usb3_wake_enable_bitmap;
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};
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};
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typedef struct soc_intel_skylake_config config_t;
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typedef struct soc_intel_skylake_config config_t;
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@ -54,7 +54,9 @@ typedef struct {
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u64 nhla; /* 0x31 - NHLT Address */
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u64 nhla; /* 0x31 - NHLT Address */
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u32 nhll; /* 0x39 - NHLT Length */
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u32 nhll; /* 0x39 - NHLT Length */
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u16 cid1; /* 0x3d - Wifi Country Identifier */
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u16 cid1; /* 0x3d - Wifi Country Identifier */
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u8 unused[193];
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u16 u2we; /* 0x3f - USB2 Wake Enable Bitmap */
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u8 u3we; /* 0x41 - USB3 Wake Enable Bitmap */
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u8 unused[190];
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/* ChromeOS specific (0x100 - 0xfff) */
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/* ChromeOS specific (0x100 - 0xfff) */
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chromeos_acpi_t chromeos;
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chromeos_acpi_t chromeos;
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@ -169,4 +169,11 @@ struct usb3_port_config {
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.tx_downscale_amp = 0x00, \
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.tx_downscale_amp = 0x00, \
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}
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}
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/*
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* Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds
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* to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to
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* decide what ports need to set PORTSCN/PORTSCXUSB3 register bits.
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*/
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#define USB_PORT_WAKE_ENABLE(x) (1 << (x - 1))
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#endif
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#endif
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