I've checked Revision Guide for AMD Family10h processors (#41322) rev
3.74 June 2010 for errata 351 and it agrees with the comment on setting ForceFullT0= 000b but I believe the code didn't honor the comment. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -161,7 +161,7 @@ static const struct {
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/* Link Global Extended Control Register */
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{ 0, 0x16C, AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
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0x00000014, 0x0000003F }, /* [15:13] ForceFullT0 = 0b,
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0x00000014, 0x0000E03F }, /* [15:13] ForceFullT0 = 0b,
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* Set T0Time 14h per BKDG */
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