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soc/intel/alderlake: remove tmp bar assignment for cpu crashlog 

When the cpu_cl_discovery is called, coreboot actually assigns a BAR
to cpu crashlog pci device. Hence, we don't need to assign a tmp BAR
for cpu crashlog pci device

BUG=b:195327879
TEST=Found BERT table is created and the tcss function is ok in depthcharge

Change-Id: Ib7e6772be51ec4f26ef31fed6cb2bddef8ffc6be
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Kane Chen 2021-11-16 09:07:16 +08:00 committed by Patrick Georgi
parent d88d2da813
commit 3c01123abb
1 changed files with 2 additions and 15 deletions
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17
src/soc/intel/alderlake/crashlog.c
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@ -210,27 +210,14 @@ bool cpu_cl_discovery(void)
m_cpu_crashLog_support = true;
/* Program BAR address and enable command register memory space decoding */
u32 tmp_bar_addr = PCH_PWRM_BASE_ADDRESS;
printk(BIOS_DEBUG, "tmp_bar_addr: 0x%X\n", tmp_bar_addr);
if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) {
pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0, tmp_bar_addr);
} else if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR1) {
pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_1, tmp_bar_addr);
} else {
printk(BIOS_DEBUG, "invalid discovery data t_bir_q: 0x%x\n",
cpu_cl_devsc_cap.discovery_data.fields.t_bir_q);
return false;
}
pci_or_config16(SA_DEV_TMT, PCI_COMMAND, PCI_COMMAND_MEMORY);
const struct resource *res = find_resource(SA_DEV_TMT, PCI_BASE_ADDRESS_0);
printk(BIOS_DEBUG, "cpu crashlog bar addr: 0x%llX\n", res->base);
if (!cpu_cl_gen_discovery_table()) {
printk(BIOS_ERR, "CPU crashlog discovery table not valid.\n");
m_cpu_crashLog_present = false;
return false;
}
m_cpu_crashLog_present = true;
return true;
}