soc/intel/alderlake: remove tmp bar assignment for cpu crashlog
When the cpu_cl_discovery is called, coreboot actually assigns a BAR to cpu crashlog pci device. Hence, we don't need to assign a tmp BAR for cpu crashlog pci device BUG=b:195327879 TEST=Found BERT table is created and the tcss function is ok in depthcharge Change-Id: Ib7e6772be51ec4f26ef31fed6cb2bddef8ffc6be Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -210,27 +210,14 @@ bool cpu_cl_discovery(void)
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m_cpu_crashLog_support = true;
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m_cpu_crashLog_support = true;
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/* Program BAR address and enable command register memory space decoding */
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const struct resource *res = find_resource(SA_DEV_TMT, PCI_BASE_ADDRESS_0);
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u32 tmp_bar_addr = PCH_PWRM_BASE_ADDRESS;
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printk(BIOS_DEBUG, "cpu crashlog bar addr: 0x%llX\n", res->base);
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printk(BIOS_DEBUG, "tmp_bar_addr: 0x%X\n", tmp_bar_addr);
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if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) {
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pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0, tmp_bar_addr);
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} else if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR1) {
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pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_1, tmp_bar_addr);
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} else {
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printk(BIOS_DEBUG, "invalid discovery data t_bir_q: 0x%x\n",
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cpu_cl_devsc_cap.discovery_data.fields.t_bir_q);
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return false;
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}
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pci_or_config16(SA_DEV_TMT, PCI_COMMAND, PCI_COMMAND_MEMORY);
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if (!cpu_cl_gen_discovery_table()) {
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if (!cpu_cl_gen_discovery_table()) {
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printk(BIOS_ERR, "CPU crashlog discovery table not valid.\n");
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printk(BIOS_ERR, "CPU crashlog discovery table not valid.\n");
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m_cpu_crashLog_present = false;
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m_cpu_crashLog_present = false;
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return false;
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return false;
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}
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}
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m_cpu_crashLog_present = true;
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return true;
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return true;
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}
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}
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