arch/x86: SSE2 implies SSE support
Change-Id: Ic9ffcfadd0cd41bb033ed2aec9fb98009dd62383 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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@ -4,7 +4,6 @@ config CPU_AMD_MODEL_10XXX
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select ARCH_VERSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select SSE
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select SSE2
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select TSC_SYNC_LFENCE
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select UDELAY_LAPIC
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@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS
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select HAVE_MONOTONIC_TIMER
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select SMP
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select MMX
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select SSE
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select SSE2
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select UDELAY_TSC
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select TSC_CONSTANT_RATE
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@ -10,7 +10,6 @@ config CPU_SPECIFIC_OPTIONS
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select SMP
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select SSE
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select SSE2
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select UDELAY_TSC
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select TSC_CONSTANT_RATE
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@ -6,7 +6,6 @@ if CPU_INTEL_SOCKET_FCBGA1023
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config SOCKET_SPECIFIC_OPTIONS # dummy
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def_bool y
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select MMX
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select SSE
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select SSE2
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endif
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@ -62,7 +62,6 @@ config CPU_SPECIFIC_OPTIONS
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select SMM_TSEG
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select POSTCAR_STAGE
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select POSTCAR_CONSOLE
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select SSE
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select SSE2
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select RTC
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select SOC_AMD_PSP_SELECTABLE_SMU_FW
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