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sb,soc/intel: Refactor power_on_after_fail option 

It's only necessary to call get_option() with SLP_TYP S5.

Change-Id: Ic821b429a58a2c0713ec338904364ec57bfbcfce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49251
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2021-01-08 19:01:30 +02:00
parent 22236a580d
commit 3c18186e76
3 changed files with 46 additions and 41 deletions
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28
src/soc/intel/broadwell/pch/smihandler.c
View File

@ -125,13 +125,9 @@ static void backlight_off(void)
printk(BIOS_INFO, "Backlight turned off\n");
}
static void southbridge_smi_sleep(void)
static int power_on_after_fail(void)
{
u8 reg8;
u32 reg32;
u8 slp_typ;
u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
u16 pmbase = get_pmbase();
/* save and recover RTC port values */
u8 tmp70, tmp72;
@ -141,6 +137,16 @@ static void southbridge_smi_sleep(void)
outb(tmp70, 0x70);
outb(tmp72, 0x72);
/* For "KEEP", switch to "OFF" - KEEP is software emulated. */
return (s5pwr == MAINBOARD_POWER_ON);
}
static void southbridge_smi_sleep(void)
{
u32 reg32;
u8 slp_typ;
u16 pmbase = get_pmbase();
/* First, disable further SMIs */
disable_smi(SLP_SMI_EN);
@ -190,15 +196,11 @@ static void southbridge_smi_sleep(void)
/* Disable all GPE */
disable_all_gpe();
/* Always set the flag in case CMOS was changed on runtime. For
* "KEEP", switch to "OFF" - KEEP is software emulated
*/
reg8 = pci_read_config8(PCH_DEV_LPC, GEN_PMCON_3);
if (s5pwr == MAINBOARD_POWER_ON)
reg8 &= ~1;
/* Always set the flag in case CMOS was changed on runtime. */
if (power_on_after_fail())
pci_and_config8(PCH_DEV_LPC, GEN_PMCON_3, ~1);
else
reg8 |= 1;
pci_write_config8(PCH_DEV_LPC, GEN_PMCON_3, reg8);
pci_or_config8(PCH_DEV_LPC, GEN_PMCON_3, 1);
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);

31
src/southbridge/intel/common/smihandler.c
View File

@ -93,14 +93,11 @@ __weak void southbridge_smm_xhci_sleep(u8 slp_type)
{
}
static void southbridge_smi_sleep(void)
static int power_on_after_fail(void)
{
u8 reg8;
u32 reg32;
u8 slp_typ;
u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
// save and recover RTC port values
/* save and recover RTC port values */
u8 tmp70, tmp72;
tmp70 = inb(0x70);
tmp72 = inb(0x72);
@ -108,6 +105,15 @@ static void southbridge_smi_sleep(void)
outb(tmp70, 0x70);
outb(tmp72, 0x72);
/* For "KEEP", switch to "OFF" - KEEP is software emulated. */
return (s5pwr == MAINBOARD_POWER_ON);
}
static void southbridge_smi_sleep(void)
{
u32 reg32;
u8 slp_typ;
/* First, disable further SMIs */
write_pmbase8(SMI_EN, read_pmbase8(SMI_EN) & ~SLP_SMI_EN);
@ -153,16 +159,11 @@ static void southbridge_smi_sleep(void)
write_pmbase32(GPE0_EN, 0);
/* Always set the flag in case CMOS was changed on runtime. For
* "KEEP", switch to "OFF" - KEEP is software emulated
*/
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), D31F0_GEN_PMCON_3);
if (s5pwr == MAINBOARD_POWER_ON) {
reg8 &= ~1;
} else {
reg8 |= 1;
}
pci_write_config8(PCI_DEV(0, 0x1f, 0), D31F0_GEN_PMCON_3, reg8);
/* Always set the flag in case CMOS was changed on runtime. */
if (power_on_after_fail())
pci_and_config8(PCI_DEV(0, 0x1f, 0), D31F0_GEN_PMCON_3, ~1);
else
pci_or_config8(PCI_DEV(0, 0x1f, 0), D31F0_GEN_PMCON_3, 1);
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);

28
src/southbridge/intel/lynxpoint/smihandler.c
View File

@ -76,13 +76,9 @@ static void busmaster_disable_on_bus(int bus)
}
}
static void southbridge_smi_sleep(void)
static int power_on_after_fail(void)
{
u8 reg8;
u32 reg32;
u8 slp_typ;
u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
u16 pmbase = get_pmbase();
/* save and recover RTC port values */
u8 tmp70, tmp72;
@ -92,6 +88,16 @@ static void southbridge_smi_sleep(void)
outb(tmp70, 0x70);
outb(tmp72, 0x72);
/* For "KEEP", switch to "OFF" - KEEP is software emulated. */
return (s5pwr == MAINBOARD_POWER_ON);
}
static void southbridge_smi_sleep(void)
{
u32 reg32;
u8 slp_typ;
u16 pmbase = get_pmbase();
/* First, disable further SMIs */
disable_smi(SLP_SMI_EN);
@ -139,15 +145,11 @@ static void southbridge_smi_sleep(void)
/* Disable all GPE */
disable_all_gpe();
/* Always set the flag in case CMOS was changed on runtime. For
* "KEEP", switch to "OFF" - KEEP is software emulated
*/
reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3);
if (s5pwr == MAINBOARD_POWER_ON)
reg8 &= ~1;
/* Always set the flag in case CMOS was changed on runtime. */
if (power_on_after_fail())
pci_and_config8(PCH_LPC_DEV, GEN_PMCON_3, ~1);
else
reg8 |= 1;
pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8);
pci_or_config8(PCH_LPC_DEV, GEN_PMCON_3, 1);
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);