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nb/intel/nehalem: Prevent out of bounds read 

If the decoded SPD DRAM frequency is slower than the controller minimum,
then there will be an unsigned integer underflow in the following loop,
which will lead to a very large out of bounds array access. Ensure this
does not happen.

Change-Id: Ic8ed1293adfe0866781bd638323977abd110777e
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229675
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Jacob Garber 2019-06-10 18:23:32 -06:00 committed by Martin Roth
parent c14eb3b950
commit 3c19382367
1 changed files with 2 additions and 0 deletions
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src/northbridge/intel/nehalem/raminit.c
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@ -595,6 +595,8 @@ static void calculate_timings(struct raminfo *info)
info-> info->
spd[channel][slot][CAS_LATENCY_TIME]); spd[channel][slot][CAS_LATENCY_TIME]);
} }
if (cycletime > min_cycletime[0])
die("RAM init: Decoded SPD DRAM freq is slower than the controller minimum!");
for (clock_speed_index = 0; clock_speed_index < 3; clock_speed_index++) { for (clock_speed_index = 0; clock_speed_index < 3; clock_speed_index++) {
if (cycletime == min_cycletime[clock_speed_index]) if (cycletime == min_cycletime[clock_speed_index])
break; break;