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soc/intel/broadwell: Use common sb code for SPI lockdown configuration 

Change-Id: I5a8239f4e9e1f9728074ff5452c95d3138965d82
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans 2019-10-13 22:54:53 +02:00 committed by Nico Huber
parent 5efee3a2c2
commit 3c1e986119
2 changed files with 3 additions and 51 deletions
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13
src/soc/intel/broadwell/finalize.c
View File

@ -27,6 +27,7 @@
#include <soc/rcba.h>
#include <soc/spi.h>
#include <soc/systemagent.h>
#include <southbridge/intel/common/spi.h>
const struct reg_script system_agent_finalize_script[] = {
REG_PCI_OR16(0x50, 1 << 0), /* GGC */
@ -57,16 +58,6 @@ const struct reg_script system_agent_finalize_script[] = {
const struct reg_script pch_finalize_script[] = {
#if !CONFIG(SPI_CONSOLE)
/* Set SPI opcode menu */
REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_PREOP,
SPI_OPPREFIX),
REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_OPTYPE,
SPI_OPTYPE),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET +
SPIBAR_OPMENU_LOWER, SPI_OPMENU_LOWER),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET +
SPIBAR_OPMENU_UPPER, SPI_OPMENU_UPPER),
/* Lock SPIBAR */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS,
SPIBAR_HSFS_FLOCKDN),
@ -101,6 +92,8 @@ static void broadwell_finalize(void *unused)
printk(BIOS_DEBUG, "Finalizing chipset.\n");
reg_script_run_on_dev(sa_dev, system_agent_finalize_script);
spi_finalize_ops();
reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script);
/* Lock */

41
src/soc/intel/broadwell/include/soc/spi.h
View File

@ -30,47 +30,6 @@
#define SPIBAR_FDOC 0xb0
#define SPIBAR_FDOD 0xb4
#define SPIBAR_PREOP 0x94
#define SPIBAR_OPTYPE 0x96
#define SPIBAR_OPMENU_LOWER 0x98
#define SPIBAR_OPMENU_UPPER 0x9c
#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
#define SPI_OPTYPE_0 0x01 /* Write, no address */
#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
#define SPI_OPTYPE_1 0x03 /* Write, address required */
#define SPI_OPMENU_2 0x03 /* READ: Read Data */
#define SPI_OPTYPE_2 0x02 /* Read, address required */
#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
#define SPI_OPTYPE_3 0x00 /* Read, no address */
#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
#define SPI_OPTYPE_4 0x03 /* Write, address required */
#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
#define SPI_OPTYPE_5 0x00 /* Read, no address */
#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
#define SPI_OPTYPE_6 0x03 /* Write, address required */
#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
#define SPI_OPTYPE_7 0x02 /* Read, address required */
#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
(SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
(SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
(SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
(SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
(SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
#define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */
#define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */