soc/intel/broadwell: Use common sb code for SPI lockdown configuration
Change-Id: I5a8239f4e9e1f9728074ff5452c95d3138965d82 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -27,6 +27,7 @@
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#include <soc/rcba.h>
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#include <soc/spi.h>
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#include <soc/systemagent.h>
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#include <southbridge/intel/common/spi.h>
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const struct reg_script system_agent_finalize_script[] = {
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REG_PCI_OR16(0x50, 1 << 0), /* GGC */
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@ -57,16 +58,6 @@ const struct reg_script system_agent_finalize_script[] = {
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const struct reg_script pch_finalize_script[] = {
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#if !CONFIG(SPI_CONSOLE)
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/* Set SPI opcode menu */
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REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_PREOP,
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SPI_OPPREFIX),
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REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_OPTYPE,
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SPI_OPTYPE),
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REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET +
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SPIBAR_OPMENU_LOWER, SPI_OPMENU_LOWER),
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REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET +
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SPIBAR_OPMENU_UPPER, SPI_OPMENU_UPPER),
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/* Lock SPIBAR */
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REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS,
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SPIBAR_HSFS_FLOCKDN),
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@ -101,6 +92,8 @@ static void broadwell_finalize(void *unused)
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printk(BIOS_DEBUG, "Finalizing chipset.\n");
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reg_script_run_on_dev(sa_dev, system_agent_finalize_script);
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spi_finalize_ops();
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reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script);
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/* Lock */
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@ -30,47 +30,6 @@
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#define SPIBAR_FDOC 0xb0
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#define SPIBAR_FDOD 0xb4
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#define SPIBAR_PREOP 0x94
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#define SPIBAR_OPTYPE 0x96
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#define SPIBAR_OPMENU_LOWER 0x98
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#define SPIBAR_OPMENU_UPPER 0x9c
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#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
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#define SPI_OPTYPE_0 0x01 /* Write, no address */
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#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
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#define SPI_OPTYPE_1 0x03 /* Write, address required */
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#define SPI_OPMENU_2 0x03 /* READ: Read Data */
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#define SPI_OPTYPE_2 0x02 /* Read, address required */
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#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
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#define SPI_OPTYPE_3 0x00 /* Read, no address */
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#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
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#define SPI_OPTYPE_4 0x03 /* Write, address required */
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#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
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#define SPI_OPTYPE_5 0x00 /* Read, no address */
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#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
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#define SPI_OPTYPE_6 0x03 /* Write, address required */
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#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
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#define SPI_OPTYPE_7 0x02 /* Read, address required */
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#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
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(SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
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#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
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(SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
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#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
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(SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
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(SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
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(SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
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#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
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#define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */
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#define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */
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