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southbridge/amd agesa & cimx spelling fixes 

Trivial fixes, but the editor highlights them, and it's easy to go
through a bunch of files while I'm otherwise idle.

Change-Id: I5d2d4ba098d2a95f7643f000f4b48b3349a8e6cf
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7839
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Martin Roth 2014-12-16 20:50:26 -07:00 committed by Martin Roth
parent 55e31a9e33
commit 3c3a50c3c4
20 changed files with 40 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/southbridge/amd/agesa/hudson/hudson.c
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@ -34,7 +34,7 @@
/* Offsets from ACPI_MMIO_BASE /* Offsets from ACPI_MMIO_BASE
* This is defined by AGESA, but we don't include AGESA headers to avoid * This is defined by AGESA, but we don't include AGESA headers to avoid
* polluting the namesace. * polluting the namespace.
*/ */
#define PM_MMIO_BASE 0xfed80300 #define PM_MMIO_BASE 0xfed80300

2
src/southbridge/amd/agesa/hudson/lpc.c
View File

@ -126,7 +126,7 @@ static void hudson_lpc_set_resources(struct device *dev)
/** /**
* @brief Enable resources for children devices * @brief Enable resources for children devices
* *
* @param dev the device whos children's resources are to be enabled * @param dev the device whose children's resources are to be enabled
* *
*/ */
static void hudson_lpc_enable_childrens_resources(device_t dev) static void hudson_lpc_enable_childrens_resources(device_t dev)

2
src/southbridge/amd/agesa/hudson/smihandler.c
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@ -65,7 +65,7 @@ static void process_gpe_smi(void)
/* Only Bits [23:0] indicate GEVENT SMIs. */ /* Only Bits [23:0] indicate GEVENT SMIs. */
if (status & gevent_mask) { if (status & gevent_mask) {
/* A GEVENT SMI occured */ /* A GEVENT SMI occurred */
if (mainboard_smi_gpi) if (mainboard_smi_gpi)
mainboard_smi_gpi(status & gevent_mask); mainboard_smi_gpi(status & gevent_mask);
} }

2
src/southbridge/amd/cimx/sb700/late.c
View File

@ -30,7 +30,7 @@
#include <device/pci_ehci.h> #include <device/pci_ehci.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include "lpc.h" /* lpc_read_resources */ #include "lpc.h" /* lpc_read_resources */
#include "Platform.h" /* Platfrom Specific Definitions */ #include "Platform.h" /* Platform Specific Definitions */
#include "sb_cimx.h" #include "sb_cimx.h"
#include "sb700_cfg.h" /* sb700 Cimx configuration */ #include "sb700_cfg.h" /* sb700 Cimx configuration */
#include "chip.h" /* struct southbridge_amd_cimx_sb700_config */ #include "chip.h" /* struct southbridge_amd_cimx_sb700_config */

6
src/southbridge/amd/cimx/sb700/lpc.c
View File

@ -89,7 +89,7 @@ void lpc_set_resources(struct device *dev)
/** /**
* @brief Enable resources for children devices * @brief Enable resources for children devices
* *
* @param dev the device whos children's resources are to be enabled * @param dev the device whose children's resources are to be enabled
* *
*/ */
void lpc_enable_childrens_resources(device_t dev) void lpc_enable_childrens_resources(device_t dev)
@ -131,13 +131,13 @@ void lpc_enable_childrens_resources(device_t dev)
case 0x2f8: /* COM2 */ case 0x2f8: /* COM2 */
reg |= (1 << 7); reg |= (1 << 7);
break; break;
case 0x378: /* Parallal 1 */ case 0x378: /* Parallel 1 */
reg |= (1 << 0); reg |= (1 << 0);
break; break;
case 0x3f0: /* FD0 */ case 0x3f0: /* FD0 */
reg |= (1 << 26); reg |= (1 << 26);
break; break;
case 0x220: /* Aduio 0 */ case 0x220: /* Audio 0 */
reg |= (1 << 8); reg |= (1 << 8);
break; break;
case 0x300: /* Midi 0 */ case 0x300: /* Midi 0 */

4
src/southbridge/amd/cimx/sb700/smbus.c
View File

@ -201,7 +201,7 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
tmp |= val; tmp |= val;
/* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */ /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */
outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we don't have to do it again. */
outl(tmp, AB_DATA); outl(tmp, AB_DATA);
outl(0, AB_INDX); outl(0, AB_INDX);
printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ab_indx - End.\n"); printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ab_indx - End.\n");
@ -224,7 +224,7 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
tmp |= val; tmp |= val;
//printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr);
outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we don't have to do it again. */
outl(tmp, AB_DATA); outl(tmp, AB_DATA);
outl(0, AB_INDX); outl(0, AB_INDX);
printk(BIOS_SPEW, "SB700 - Smbus.c - alink_rc_indx - End.\n"); printk(BIOS_SPEW, "SB700 - Smbus.c - alink_rc_indx - End.\n");

4
src/southbridge/amd/cimx/sb800/SBPLATFORM.h
View File

@ -73,7 +73,7 @@ typedef union _PCI_ADDR {
//------------------------------------------------------------------------------------------------------------------------// //------------------------------------------------------------------------------------------------------------------------//
/** /**
* SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over * SB_CIMx_PARAMETER 0 1 2 Default Value When CIMx Take over
* SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable
* SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal
* HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable
@ -91,7 +91,7 @@ typedef union _PCI_ADDR {
* GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
* UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable
* SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable
* SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11) * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Never Power down (0x11)
* SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00) * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00)
* SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz
* SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable

2
src/southbridge/amd/cimx/sb800/cfg.c
View File

@ -71,7 +71,7 @@ unsigned long get_top_of_ram(void)
/** /**
* @brief South Bridge CIMx configuration * @brief South Bridge CIMx configuration
* *
* should be called before exeucte CIMx function. * should be called before executing CIMx functions.
* this function will be called in romstage and ramstage. * this function will be called in romstage and ramstage.
*/ */
void sb800_cimx_config(AMDSBCFG *sb_config) void sb800_cimx_config(AMDSBCFG *sb_config)

2
src/southbridge/amd/cimx/sb800/early.c
View File

@ -58,7 +58,7 @@ void sb_Poweron_Init(void)
//AmdSbDispatcher(&sb_early_cfg); //AmdSbDispatcher(&sb_early_cfg);
//TODO //TODO
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
// VerifyImage() will fail, LocateImage() take minitues to find the image. // VerifyImage() will fail, LocateImage() take minutes to find the image.
sbPowerOnInit(&sb_early_cfg); sbPowerOnInit(&sb_early_cfg);
} }

2
src/southbridge/amd/cimx/sb800/fadt.c
View File

@ -125,7 +125,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ fadt->duty_width = 3; /* CLK_VAL bits 3:1 */
fadt->day_alrm = 0; /* 0x7d these have to be */ fadt->day_alrm = 0; /* 0x7d these have to be */
fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
fadt->century = 0; /* 0x7f to make rtc alrm work */ fadt->century = 0; /* 0x7f to make rtc alarm work */
fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */ fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */
fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */
fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */

10
src/southbridge/amd/cimx/sb800/fan.c
View File

@ -222,7 +222,7 @@ if (sb_chip->imc_fan_zone3_enabled) {
} }
/* /*
* EC LDN9 funtion 89 - Set HWM TEMPIN Temperature Calculation Parameters * EC LDN9 function 89 - Set HWM TEMPIN Temperature Calculation Parameters
* This function provides the critical parameters of the HWM TempIn * This function provides the critical parameters of the HWM TempIn
* sensors, IMC would not perform temperature measurement using those * sensors, IMC would not perform temperature measurement using those
* sensors until the parameters are provided. * sensors until the parameters are provided.
@ -232,7 +232,7 @@ if (sb_chip->imc_tempin0_enabled) {
sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN0; sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN0;
/* EC LDN9 funtion 89 TEMPIN channel 0 */ /* EC LDN9 function 89 TEMPIN channel 0 */
sb_config.Pecstruct.MSGFun89zone0MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun89zone0MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun89zone0MSGREG1 = 0x00; sb_config.Pecstruct.MSGFun89zone0MSGREG1 = 0x00;
sb_config.Pecstruct.MSGFun89zone0MSGREG2 = ( sb_chip->imc_tempin0_at & 0xff); sb_config.Pecstruct.MSGFun89zone0MSGREG2 = ( sb_chip->imc_tempin0_at & 0xff);
@ -250,7 +250,7 @@ if (sb_chip->imc_tempin1_enabled) {
sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN1; sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN1;
/* EC LDN9 funtion 89 TEMPIN channel 1 */ /* EC LDN9 function 89 TEMPIN channel 1 */
sb_config.Pecstruct.MSGFun89zone1MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun89zone1MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun89zone1MSGREG1 = 0x01; sb_config.Pecstruct.MSGFun89zone1MSGREG1 = 0x01;
sb_config.Pecstruct.MSGFun89zone1MSGREG2 = ( sb_chip->imc_tempin1_at & 0xff); sb_config.Pecstruct.MSGFun89zone1MSGREG2 = ( sb_chip->imc_tempin1_at & 0xff);
@ -268,7 +268,7 @@ if (sb_chip->imc_tempin2_enabled) {
sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN2; sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN2;
/* EC LDN9 funtion 89 TEMPIN channel 2 */ /* EC LDN9 function 89 TEMPIN channel 2 */
sb_config.Pecstruct.MSGFun89zone2MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun89zone2MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun89zone2MSGREG1 = 0x02; sb_config.Pecstruct.MSGFun89zone2MSGREG1 = 0x02;
sb_config.Pecstruct.MSGFun89zone2MSGREG2 = ( sb_chip->imc_tempin2_at & 0xff); sb_config.Pecstruct.MSGFun89zone2MSGREG2 = ( sb_chip->imc_tempin2_at & 0xff);
@ -286,7 +286,7 @@ if (sb_chip->imc_tempin3_enabled) {
sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN3; sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN3;
/* EC LDN9 funtion 89 TEMPIN channel 3 */ /* EC LDN9 function 89 TEMPIN channel 3 */
sb_config.Pecstruct.MSGFun89zone3MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun89zone3MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun89zone3MSGREG1 = 0x03; sb_config.Pecstruct.MSGFun89zone3MSGREG1 = 0x03;
sb_config.Pecstruct.MSGFun89zone3MSGREG2 = ( sb_chip->imc_tempin3_at & 0xff); sb_config.Pecstruct.MSGFun89zone3MSGREG2 = ( sb_chip->imc_tempin3_at & 0xff);

2
src/southbridge/amd/cimx/sb800/late.c
View File

@ -32,7 +32,7 @@
#include <arch/acpi.h> #include <arch/acpi.h>
#include <device/pci_ehci.h> #include <device/pci_ehci.h>
#include "lpc.h" /* lpc_read_resources */ #include "lpc.h" /* lpc_read_resources */
#include "SBPLATFORM.h" /* Platfrom Specific Definitions */ #include "SBPLATFORM.h" /* Platform Specific Definitions */
#include "cfg.h" /* sb800 Cimx configuration */ #include "cfg.h" /* sb800 Cimx configuration */
#include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ #include "chip.h" /* struct southbridge_amd_cimx_sb800_config */
#include "sb_cimx.h" /* AMD CIMX wrapper entries */ #include "sb_cimx.h" /* AMD CIMX wrapper entries */

6
src/southbridge/amd/cimx/sb800/lpc.c
View File

@ -77,7 +77,7 @@ void lpc_set_resources(struct device *dev)
/** /**
* @brief Enable resources for children devices * @brief Enable resources for children devices
* *
* @param dev the device whos children's resources are to be enabled * @param dev the device whose children's resources are to be enabled
* *
*/ */
void lpc_enable_childrens_resources(device_t dev) void lpc_enable_childrens_resources(device_t dev)
@ -119,13 +119,13 @@ void lpc_enable_childrens_resources(device_t dev)
case 0x2f8: /* COM2 */ case 0x2f8: /* COM2 */
reg |= (1 << 7); reg |= (1 << 7);
break; break;
case 0x378: /* Parallal 1 */ case 0x378: /* Parallel 1 */
reg |= (1 << 0); reg |= (1 << 0);
break; break;
case 0x3f0: /* FD0 */ case 0x3f0: /* FD0 */
reg |= (1 << 26); reg |= (1 << 26);
break; break;
case 0x220: /* Aduio 0 */ case 0x220: /* Audio 0 */
reg |= (1 << 8); reg |= (1 << 8);
break; break;
case 0x300: /* Midi 0 */ case 0x300: /* Midi 0 */

4
src/southbridge/amd/cimx/sb800/smbus.c
View File

@ -205,7 +205,7 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
tmp |= val; tmp |= val;
/* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */ /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */
outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we don't have to do it again. */
outl(tmp, AB_DATA); outl(tmp, AB_DATA);
outl(0, AB_INDX); outl(0, AB_INDX);
printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ab_indx - End.\n"); printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ab_indx - End.\n");
@ -228,7 +228,7 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
tmp |= val; tmp |= val;
//printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr);
outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we don't have to do it again. */
outl(tmp, AB_DATA); outl(tmp, AB_DATA);
outl(0, AB_INDX); outl(0, AB_INDX);
printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_rc_indx - End.\n"); printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_rc_indx - End.\n");

4
src/southbridge/amd/cimx/sb900/SbPlatform.h
View File

@ -70,7 +70,7 @@ typedef union _PCI_ADDR {
//------------------------------------------------------------------------------------------------------------------------// //------------------------------------------------------------------------------------------------------------------------//
/** /**
* SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over * SB_CIMx_PARAMETER 0 1 2 Default Value When CIMx Take over
* SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable
* SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal
* HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable
@ -88,7 +88,7 @@ typedef union _PCI_ADDR {
* GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
* UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable
* SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable
* SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11) * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Never Power down (0x11)
* SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00) * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00)
* SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz
* SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable

4
src/southbridge/amd/cimx/sb900/cfg.c
View File

@ -26,7 +26,7 @@
/** /**
* @brief South Bridge CIMx configuration * @brief South Bridge CIMx configuration
* *
* should be called before exeucte CIMx function. * should be called before execute CIMx function.
* this function will be called in romstage and ramstage. * this function will be called in romstage and ramstage.
*/ */
void sb900_cimx_config(AMDSBCFG *sb_config) void sb900_cimx_config(AMDSBCFG *sb_config)
@ -274,7 +274,7 @@ void SbPowerOnInit_Config(AMDSBCFG *sb_config)
sb_config->BuildParameters.SpiFastSpeed = SBCIMX_SPI_FASTSPEED; // Internal Option sb_config->BuildParameters.SpiFastSpeed = SBCIMX_SPI_FASTSPEED; // Internal Option
// sb_config->BuildParameters.SpiWriteSpeed = 0; // Field Retired // sb_config->BuildParameters.SpiWriteSpeed = 0; // Field Retired
sb_config->BuildParameters.SpiMode = SBCIMX_SPI_MODE; // Internal Option sb_config->BuildParameters.SpiMode = SBCIMX_SPI_MODE; // Internal Option
sb_config->BuildParameters.SpiBurstWrite = SBCIMX_SPI_BURST_WRITE; // Internla Option sb_config->BuildParameters.SpiBurstWrite = SBCIMX_SPI_BURST_WRITE; // Internal Option
sb_config->BuildParameters.EcKbd = INCHIP_EC_KBD; // Board Level sb_config->BuildParameters.EcKbd = INCHIP_EC_KBD; // Board Level
sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; // Board Level sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; // Board Level
sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; // Board Level sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; // Board Level

10
src/southbridge/amd/cimx/sb900/early.c
View File

@ -74,7 +74,7 @@ void sb_poweron_init(void)
//AmdSbDispatcher(&sb_early_cfg); //AmdSbDispatcher(&sb_early_cfg);
//TODO //TODO
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
// VerifyImage() will fail, LocateImage() take minitues to find the image. // VerifyImage() will fail, LocateImage() take minutes to find the image.
sbPowerOnInit(&sb_early_cfg); sbPowerOnInit(&sb_early_cfg);
printk(BIOS_SPEW, "SB900 - Early.c - sb_poweron_init - End.\n"); printk(BIOS_SPEW, "SB900 - Early.c - sb_poweron_init - End.\n");
} }
@ -93,7 +93,7 @@ void sb_before_pci_init(void)
//AmdSbDispatcher(&sb_early_cfg); //AmdSbDispatcher(&sb_early_cfg);
//TODO //TODO
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
// VerifyImage() will fail, LocateImage() take minitues to find the image. // VerifyImage() will fail, LocateImage() take minutes to find the image.
sbBeforePciInit(&sb_early_cfg); sbBeforePciInit(&sb_early_cfg);
printk(BIOS_SPEW, "SB900 - Early.c - sb_before_pci_init - End.\n"); printk(BIOS_SPEW, "SB900 - Early.c - sb_before_pci_init - End.\n");
} }
@ -109,7 +109,7 @@ void sb_After_Pci_Init(void)
//AmdSbDispatcher(&sb_early_cfg); //AmdSbDispatcher(&sb_early_cfg);
//TODO //TODO
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
// VerifyImage() will fail, LocateImage() take minitues to find the image. // VerifyImage() will fail, LocateImage() take minutes to find the image.
sbAfterPciInit(&sb_early_cfg); sbAfterPciInit(&sb_early_cfg);
printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - End.\n"); printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - End.\n");
#endif #endif
@ -125,7 +125,7 @@ void sb_Mid_Post_Init(void)
//AmdSbDispatcher(&sb_early_cfg); //AmdSbDispatcher(&sb_early_cfg);
//TODO //TODO
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
// VerifyImage() will fail, LocateImage() take minitues to find the image. // VerifyImage() will fail, LocateImage() take minutes to find the image.
sbMidPostInit(&sb_early_cfg); sbMidPostInit(&sb_early_cfg);
printk(BIOS_SPEW, "SB900 - Early.c - sb_Mid_Post_Init - End.\n"); printk(BIOS_SPEW, "SB900 - Early.c - sb_Mid_Post_Init - End.\n");
} }
@ -142,7 +142,7 @@ void sb_Late_Post(void)
//AmdSbDispatcher(&sb_early_cfg); //AmdSbDispatcher(&sb_early_cfg);
//TODO //TODO
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
// VerifyImage() will fail, LocateImage() take minitues to find the image. // VerifyImage() will fail, LocateImage() take minutes to find the image.
sbLatePost(&sb_early_cfg); sbLatePost(&sb_early_cfg);
//Set ACPI SCI IRQ to 0x9. //Set ACPI SCI IRQ to 0x9.

2
src/southbridge/amd/cimx/sb900/late.c
View File

@ -29,7 +29,7 @@
#include <device/pci_ehci.h> #include <device/pci_ehci.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include "lpc.h" /* lpc_read_resources */ #include "lpc.h" /* lpc_read_resources */
#include "SbPlatform.h" /* Platfrom Specific Definitions */ #include "SbPlatform.h" /* Platform Specific Definitions */
#include "chip.h" /* struct southbridge_amd_cimx_sb900_config */ #include "chip.h" /* struct southbridge_amd_cimx_sb900_config */

6
src/southbridge/amd/cimx/sb900/lpc.c
View File

@ -74,7 +74,7 @@ void lpc_set_resources(struct device *dev)
/** /**
* @brief Enable resources for children devices * @brief Enable resources for children devices
* *
* @param dev the device whos children's resources are to be enabled * @param dev the device whose children's resources are to be enabled
* *
*/ */
void lpc_enable_childrens_resources(device_t dev) void lpc_enable_childrens_resources(device_t dev)
@ -116,13 +116,13 @@ void lpc_enable_childrens_resources(device_t dev)
case 0x2f8: /* COM2 */ case 0x2f8: /* COM2 */
reg |= (1 << 7); reg |= (1 << 7);
break; break;
case 0x378: /* Parallal 1 */ case 0x378: /* Parallel 1 */
reg |= (1 << 0); reg |= (1 << 0);
break; break;
case 0x3f0: /* FD0 */ case 0x3f0: /* FD0 */
reg |= (1 << 26); reg |= (1 << 26);
break; break;
case 0x220: /* Aduio 0 */ case 0x220: /* Audio 0 */
reg |= (1 << 8); reg |= (1 << 8);
break; break;
case 0x300: /* Midi 0 */ case 0x300: /* Midi 0 */

4
src/southbridge/amd/cimx/sb900/smbus.c
View File

@ -205,7 +205,7 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
tmp |= val; tmp |= val;
/* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */ /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */
outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we don't have to do it again. */
outl(tmp, AB_DATA); outl(tmp, AB_DATA);
outl(0, AB_INDX); outl(0, AB_INDX);
printk(BIOS_INFO, "SB900 - Smbus.c - alink_ab_indx - End.\n"); printk(BIOS_INFO, "SB900 - Smbus.c - alink_ab_indx - End.\n");
@ -228,7 +228,7 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
tmp |= val; tmp |= val;
//printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr);
outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we don't have to do it again. */
outl(tmp, AB_DATA); outl(tmp, AB_DATA);
outl(0, AB_INDX); outl(0, AB_INDX);
printk(BIOS_INFO, "SB900 - Smbus.c - alink_rc_indx - End.\n"); printk(BIOS_INFO, "SB900 - Smbus.c - alink_rc_indx - End.\n");