armv8/secmon: Correct PSCI function ids
PSCI_CPU_OFF is SMC32 call, there is not SMC64 version. Register SMC32 and SMC64 types of PSCI calls. BUG=None BRANCH=None TEST=Compiles successfully and CPU off works fine with PSCI command. Change-Id: I8df2eabfff52924625426b3607720c5219d38b58 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9228c07f9d9a4dd6325afb1f64b41b9b8711b146 Original-Change-Id: I2f387291893c1acf40bb6aa26f3d2ee8d5d843ea Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265622 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9925 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -368,7 +368,7 @@ static int psci_handler(struct smc_call *smc)
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case PSCI_CPU_ON64:
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psci_cpu_on(pf);
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break;
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case PSCI_CPU_OFF64:
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case PSCI_CPU_OFF32:
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psci32_return(pf, psci_turn_off_self());
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break;
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default:
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@ -563,7 +563,12 @@ void psci_init(uintptr_t cpu_on_entry)
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printk(BIOS_ERR, "Error linking cpu_info to PSCI nodes.\n");
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/* Register PSCI handlers. */
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if (smc_register_range(PSCI_CPU_OFF64, PSCI_CPU_ON64, &psci_handler))
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if (smc_register_range(PSCI_CPU_SUSPEND32, PSCI_CPU_ON32,
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&psci_handler))
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printk(BIOS_ERR, "Couldn't register PSCI handler.\n");
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if (smc_register_range(PSCI_CPU_SUSPEND64, PSCI_CPU_ON64,
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&psci_handler))
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printk(BIOS_ERR, "Couldn't register PSCI handler.\n");
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/* Inform SoC layer of CPU_ON entry point. */
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@ -164,7 +164,6 @@ enum {
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/* 64-bit CPU support functions. */
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PSCI_CPU_SUSPEND64 = SMC_FUNC_FAST64(0x4, 0x1),
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PSCI_CPU_OFF64 = SMC_FUNC_FAST64(0x4, 0x2),
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PSCI_CPU_ON64 = SMC_FUNC_FAST64(0x4, 0x3),
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};
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