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mb/google/volteer: Enable external bypass, clkgate & phygate 

This change sets the soc config options for external_bypass,
external_clk_gate and external_phy_gate.

BUG=b:177821896
TEST=Build coreboot for volteer

Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: I9e5218cda79d7453bf830639ccea4e5be019b070
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50290
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shreesh Chhabbi 2021-02-04 13:16:24 -08:00 committed by Patrick Georgi
parent fbad99f347
commit 3c6ad8d184
1 changed files with 9 additions and 0 deletions
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9
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
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@ -255,6 +255,15 @@ chip soc/intel/tigerlake
# Enable DPTF # Enable DPTF
register "dptf_enable" = "1" register "dptf_enable" = "1"
# Enable External Bypass
register "external_bypass" = "1"
# Enable External Clk Gate
register "external_clk_gated" = "1"
# Enable External Phy Gate
register "external_phy_gated" = "1"
register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
.tdp_pl1_override = 15, .tdp_pl1_override = 15,
.tdp_pl2_override = 38, .tdp_pl2_override = 38,