libpayload/xhci: Try harder to read 32-bit caps at once

With commit 287cf6c7d1 (lp/drivers/usb: Work around QEMU XHCI
register issue) we restructured our capability register accesses
because the compiler used the wrong access size. While we do use
only 32-bit types now, a compiler may still try to be clever and
optimize things in unexpected ways. So we add an explicit read32()
now.

For instance for the 8-bit MaxPorts field, in the most significant
bits of `capreg + 4`, our read + mask + shift

    ((cap)->hciparams1 & 0xff000000) >> 24

was turned into a single 8-bit read instruction by GCC on x86:

      31:   0f b6 52 07             movzbl 0x7(%edx),%edx

Change-Id: I76accd0ef718e70ca46807eb06a9177c3afd99f1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>

payloads/libpayload/drivers/usb/xhci_private.h

@@ -363,7 +363,7 @@ typedef struct erst_entry {
 #define CAP_CSZ_LEN			1
 
 #define CAP_MASK(tok)		MASK(CAP_##tok##_START, CAP_##tok##_LEN)
-#define CAP_GET(tok, cap)	(((cap)->CAP_##tok##_FIELD & CAP_MASK(tok)) \
+#define CAP_GET(tok, cap)	((read32(&(cap)->CAP_##tok##_FIELD) & CAP_MASK(tok)) \
 				 >> CAP_##tok##_START)
 
 #define CTXSIZE(xhci) (CAP_GET(CSZ, (xhci)->capreg) ? 64 : 32)