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google/eve: Adjust DPTF parameters 

- Remove the 0mA entry for the charger performance table
- Slightly raise the passive limit for TSR2/TSR3 to 55C

BUG=chrome-os-partner:58666
TEST=manual testing on P1 system

Change-Id: I75c66afe04afbbdb64a45833eb938e57ff21b392
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18172
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2017-01-18 14:31:59 -08:00 committed by Martin Roth
parent cdb93a5922
commit 3c78eae369
1 changed files with 2 additions and 3 deletions
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5
src/mainboard/google/eve/acpi/dptf.asl
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@ -29,12 +29,12 @@
#define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_ID 3
#define DPTF_TSR2_SENSOR_NAME "DRAM" #define DPTF_TSR2_SENSOR_NAME "DRAM"
#define DPTF_TSR2_PASSIVE 50 #define DPTF_TSR2_PASSIVE 55
#define DPTF_TSR2_CRITICAL 75 #define DPTF_TSR2_CRITICAL 75
#define DPTF_TSR3_SENSOR_ID 4 #define DPTF_TSR3_SENSOR_ID 4
#define DPTF_TSR3_SENSOR_NAME "eMMC" #define DPTF_TSR3_SENSOR_NAME "eMMC"
#define DPTF_TSR3_PASSIVE 50 #define DPTF_TSR3_PASSIVE 55
#define DPTF_TSR3_CRITICAL 75 #define DPTF_TSR3_CRITICAL 75
#undef DPTF_ENABLE_FAN_CONTROL #undef DPTF_ENABLE_FAN_CONTROL
@ -46,7 +46,6 @@ Name (CHPS, Package () {
Package () { 0, 0, 0, 0, 24, 0x800, "mA", 0 }, /* 2000mA */ Package () { 0, 0, 0, 0, 24, 0x800, "mA", 0 }, /* 2000mA */
Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1000mA */ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1000mA */
Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 500mA */ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 500mA */
Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0mA */
}) })
Name (DTRT, Package () { Name (DTRT, Package () {